RF Switch Circuit Topology for High Breakdown and Low Insertion Loss

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Solution Overview

Problem

Existing switch circuits for multiband communication systems face challenges in maintaining low loss while achieving high breakdown voltage, particularly when handling high-power, high-voltage radio frequency signals, as the breakdown voltage of FETs becomes a limiting factor and increasing the number of stacked FETs increases ON resistance and insertion loss.

Innovation Solution

A switch circuit configuration that includes transistors and capacitive/inductive elements to manage voltage distribution and impedance, allowing for reduced voltage across transistors and minimizing loss, with capacitive elements in series with transistors to divide voltage and inductive elements forming parallel resonant circuits to optimize power transmission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If multiple FETs are stacked in series to increase breakdown voltage, then the breakdown voltage capability is improved, but the ON resistance increases and insertion loss increases

Engineering Contradiction:
Improvebreakdown voltage capabilityVSAvoidinsertion loss
Core Design Contradiction:
StrengthVSLoss of energy

Solution Approach 1:

A capacitive element is introduced as an intermediary component connected between the first node and ground. This capacitor divides the voltage across the transistors, reducing the voltage burden on each individual FET while maintaining the overall breakdown voltage capability. The capacitor acts as a voltage distribution mediator that allows the use of fewer FETs in series, thereby reducing ON resistance and insertion loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the voltage distribution parameters by introducing the capacitive element. The capacitor's reactance at the operating frequency creates a voltage division effect, altering how the total voltage is distributed across the transistor stack. This parameter change allows for optimized voltage sharing that reduces the required number of series FETs while maintaining adequate breakdown voltage margins.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the breakdown voltage of FETs is increased to handle high-power signals, then the reliability is improved, but the ON resistance increases causing higher insertion loss

Engineering Contradiction:
Improvebreakdown voltage marginVSAvoidinsertion loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The capacitive element serves as a voltage distribution intermediary that protects the FETs from excessive voltage stress during high-power operation. By dividing the voltage across the capacitor and transistor combination, the FETs operate with adequate voltage margins for reliability without requiring excessive breakdown voltage ratings that would increase ON resistance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If a simple switch circuit configuration is used, then the device complexity is reduced, but the voltage distribution across transistors becomes unbalanced leading to breakdown risks

Engineering Contradiction:
Improvecircuit configuration simplicityVSAvoidvoltage distribution balance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The capacitive element is added to the basic switch circuit configuration to provide voltage distribution balance. This single additional component creates a voltage division mechanism that prevents any single FET from experiencing excessive voltage stress, thereby improving reliability without significantly increasing overall circuit complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The capacitive element introduces a frequency-dependent impedance that changes the voltage distribution parameters across the transistor stack. At the operating frequency, the capacitor's reactance creates an optimized voltage division ratio that balances the voltage stress on each FET, improving reliability while maintaining circuit simplicity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed configuration enhances breakdown voltage capability without compromising low loss properties, reducing the risk of transistor breakdown and minimizing insertion loss by effectively managing voltage distribution and impedance across the switch circuit.

Implementation Method 1

a capacitive element placed in the second path, the capacitive element being connected in series to the third transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

inductive elements forming parallel resonant circuits to optimize power transmission efficiency

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS11967977B2Switch circuit, radio frequency front-end circuit, and communication device
Publication Date: 2024.04.23 MURATA MFG CO LTD
  • US11967977B2 patent drawing
  • US11967977B2 patent drawing
  • US11967977B2 patent drawing

AI summary

A switch circuit (10) includes: a transistor (T1) switching the conductivity state between a drain terminal (D1) and a source terminal (S1) between being conductive and non-conductive; a transistor (T2) switching the conductivity state between a drain terminal (D2) and a source terminal (S2) between being conductive and non-conductive, the source terminals (S1) and (S2) being connected to a node (N1) and an input/output terminal (120), respectively, and the drain terminals (D1) and (D2) being connected to an input/output terminal (110) and the node (N1) respectively; a transistor (T3) switching the conductivity state between a drain terminal (D3) and a source terminal (S3) between being conductive and non-conductive, the drain terminal (D3) and the source terminal (S3) being arranged along a second path connecting the node (N1) and ground; and a capacitor (C1) placed in the second path and connected in series to the transistor (T3).