Multi-Level RF Switch Buffers for Faster FET Gate Biasing
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Solution Overview
Problem
Existing RF switching circuits face delays in turn-on and turn-off times due to high resistance gate resistors, which while providing benefits like low loss and wideband operation, degrade switching performance by increasing switching time.
Innovation Solution
A multi-level buffer system that pulses the switch control voltage using different clock signal phases and supply voltages, controlling transistor junction voltages within safe limits to speed up switching without damaging the switches, and operates using standard voltage FETs to avoid high voltage fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high resistance gate resistors are used, then low loss and wideband operation are achieved, but switching time increases
Solution Approach 1:
The patent applies periodic action by using multi-phase clock signals to periodically charge and discharge the gate resistor. The buffer circuit generates multiple clock phases (e.g., 5-phase or 7-phase) that sequentially activate different transistor paths, creating periodic current pulses through the gate resistor. This periodic charging/discharging mechanism reduces the effective RC time constant compared to DC switching, thereby shortening switching time while maintaining the high resistance value needed for low loss and wideband operation.
Solution Approach 2:
The patent changes the electrical parameters of the gate drive circuit by using variable resistance paths controlled by the multi-phase clock signals. During different phases of the clock cycle, different transistor combinations are activated, dynamically changing the effective resistance seen by the gate. This parameter modulation allows the system to achieve fast switching (low effective resistance during transitions) while maintaining low loss operation (high resistance during steady state).
2Loss of time
If voltage pulses are applied to shorten switching delay, then switching speed improves, but transistor junction voltages may be exceeded
Solution Approach 1:
The patent segments the voltage pulse generation into multiple controlled phases using different clock signals. Instead of applying a single high-voltage pulse that could exceed junction ratings, the buffer circuit divides the switching action into sequential steps across multiple transistor paths. Each phase applies a controlled voltage increment through different transistor combinations, ensuring that no single transistor junction experiences excessive voltage stress while collectively achieving the desired fast switching effect.
Solution Approach 2:
The multi-phase clock buffer circuit acts as an intermediary between the control signal and the gate resistor. It mediates the voltage application by translating a single control signal into multiple phased voltage outputs that sequentially drive different transistor paths. This intermediary mechanism ensures that voltage pulses are applied in a controlled manner that speeds up switching without directly subjecting any single transistor junction to excessive voltage, as the buffer circuit absorbs and distributes the voltage stress across multiple devices and time phases.
Data Source
AI summary
Multi-level buffers for biasing of radio frequency (RF) switches are provided. An RF switching circuit that includes a field-effect transistor (FET) switch, an impedance, and a multi-level buffer that provides a switch control voltage to a gate of the FET through the impedance is disclosed. The multi-level buffer receives a control signal to turn on or off the FET switch. Additionally, the multi-level buffer is implemented with stacked inverters that operate using different clock signal phases to pulse the switch control voltage in response to a transition of the control signal to thereby shorten a delay in switching the FET switch.