RF Switch Stack Gate-Body Filters for Equipotential Linearity
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Solution Overview
Problem
Conventional RF switch stacks in mobile phone RF front end circuitry suffer from poor linearity and power handling due to voltage imbalance and capacitance imbalance between equipotential nodes, which can be exacerbated by parasitic capacitance and common-mode current through bias resistors.
Innovation Solution
The implementation of filtration circuitry, including capacitive-based (C-based) and resistive-capacitive-based (RC-based) body and gate filters in each unit cell of the switch stack, which helps maintain equipotential nodes and reduce voltage and capacitance imbalances, thereby promoting high linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of FETs in the stack is increased to improve linearity and power handling capability, then linearity and power handling are improved, but RF loss increases and manufacturing economy decreases
Solution Approach 1:
The patent extracts and removes the parasitic capacitance effects from the system by implementing compensation networks that actively cancel out the harmful parasitic capacitance between FETs. This allows achieving better linearity without proportionally increasing the number of FETs, thereby reducing RF loss compared to simply adding more FETs to the stack.
Solution Approach 2:
The patent changes the electrical parameters of the FETs by implementing body biasing and gate compensation networks that modify the effective capacitance values. By dynamically adjusting bias conditions and compensation parameters, the system achieves improved linearity without requiring a proportional increase in the number of FETs, thus avoiding the associated RF loss penalty.
2Reliability
If the number of FETs in the stack is increased to improve power handling capability, then power handling capability is improved, but manufacturing economy decreases
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effects that limit power handling capability, allowing existing FETs to operate more efficiently. By removing these parasitic effects through compensation networks, the system achieves better power handling without needing to add more FETs, thereby maintaining manufacturing economy.
Solution Approach 2:
The patent modifies the electrical parameters of the FET stack through body biasing and gate compensation, effectively changing the voltage distribution and capacitance characteristics. This allows the existing FET configuration to handle higher power levels by optimizing parameter conditions rather than simply adding more devices, thus preserving manufacturing economy.
3Object-generated harmful factors
If parasitic capacitance and common-mode current through bias resistors are present, then voltage imbalance between equipotential nodes occurs, but linearity deteriorates
Solution Approach 1:
The patent converts the harmful parasitic capacitance and common-mode current effects into beneficial compensation opportunities. By deliberately designing compensation networks that mirror the parasitic effects, the system uses these harmful factors as reference points for cancellation, thereby restoring voltage balance and improving linearity.
Solution Approach 2:
The patent introduces compensation networks as intermediary elements between the FETs and the signal path. These intermediary networks actively counterbalance the parasitic capacitance and common-mode currents, mediating the voltage imbalance and restoring equipotential conditions without requiring fundamental changes to the FET stack architecture.
4Reliability
If filtration circuitry is added to maintain equipotential nodes and reduce voltage/capacitance imbalances, then linearity is improved, but device complexity increases
Solution Approach 1:
The patent merges the filtration and compensation functions into the existing biasing networks. By combining the body biasing circuitry with capacitance compensation elements and integrating gate compensation into the gate bias network, the system achieves voltage balance and linearity improvement without adding separate, independent filtration stages, thus limiting the increase in device complexity.
Solution Approach 2:
The patent implements multi-functional biasing networks that simultaneously provide biasing, filtration, and compensation functions. The same circuit elements serve multiple purposes: body bias resistors also function as part of the compensation network, and gate bias circuits simultaneously control switching and provide capacitance balancing, thereby reducing overall device complexity compared to dedicated separate circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the linearity and power handling capabilities of RF switch stacks by minimizing voltage and capacitance imbalances, leading to improved performance in RF front end circuitry.
Implementation Method 1
capacitive-based (C-based) and resistive-capacitive-based (RC-based) body and gate filters
Implementation Method 2
voltage imbalance and capacitance imbalance between equipotential nodes, which can be exacerbated by parasitic capacitance
Implementation Method 3
resistive-capacitive-based (RC-based) body and gate filters
Implementation Method 4
common-mode current through bias resistors
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A device for switching a radio frequency (RF) signal includes two or more field-effect transistor (FET) unit cells in a stacked or chain topology, and gate or body node filtration circuitry that preserves RF equipotential nodes. The filtration circuitry may be capacitive or resistive-capacitive. The filtration circuitry may be included in each unit cell of the device or in a gate or body bias network that is common to all unit cells in the device.