RF Switching Device with Symmetric FET Compensation
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Solution Overview
Problem
RF switches using field effect transistors (FETs) face issues with parasitic capacitance and harmonic distortion, especially at low frequencies, due to asymmetric connections and high frequency bridges that fail to handle low frequency signals effectively, leading to non-linear distortions and blocked signals.
Innovation Solution
A switching device comprising an even number of FETs on a common semiconductor substrate, where the first source region is directly connected to the second drain region, creating a common node and compensating parasitic capacitance, allowing symmetric operation and reducing harmonic distortion across a wide frequency range from DC to microwave frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a high frequency bridge (series connection of resistor and capacitor) is used to avoid parasitic capacitance, then parasitic capacitance is reduced, but low frequency signals are blocked
Solution Approach 1:
The patent employs asymmetric connection of FET channels to different voltage potentials (first voltage potential for odd-numbered channels, second voltage potential for even-numbered channels), creating a symmetric overall structure that compensates parasitic capacitance while maintaining low-frequency signal passage
Solution Approach 2:
The patent changes the voltage potential parameter applied to different FET channels, alternating between first and second voltage potentials, which transforms the parasitic capacitance characteristics to achieve compensation across the frequency spectrum including low frequencies
2Device complexity
If FET channels are asymmetrically connected to a specific voltage potential (ground), then the structure is simplified, but parasitic capacitance increases and non-linear distortions occur
Solution Approach 1:
Individual FET channels are asymmetrically connected to different voltage potentials (alternating between first and second potentials), which when viewed collectively creates a symmetric compensation effect that reduces parasitic capacitance and non-linear distortions
Solution Approach 2:
The patent converts the harmful parasitic capacitance of individual FETs into a beneficial compensation effect by alternately connecting channels to different voltage potentials, causing parasitic capacitances to cancel each other out and reduce total harmonic distortion
3Object-affected harmful factors
If an even number of FETs are used with alternating voltage potentials, then parasitic capacitance is compensated and harmonic distortion is reduced, but device complexity increases
Solution Approach 1:
The patent segments the FET channels into odd-numbered and even-numbered groups, applying different voltage potentials to each group, which enables parasitic capacitance compensation while maintaining a systematic and manageable structure
Solution Approach 2:
The alternating voltage potential configuration serves multiple functions simultaneously: it compensates parasitic capacitance, reduces harmonic distortion, maintains low-frequency signal passage, and provides a scalable architecture for power combining
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low harmonic distortion, constant resistance over frequency, and high power handling with spike-free switching, enhancing the RF switch's linearity and power quality, while simplifying manufacturing and reducing parasitic effects.
Implementation Method 1
the first source region of the first transistor is directly connected to the second drain region of the second field effect transistor to build a common node of the switching device... compensating parasitic capacitance
Data Source
AI summary
The invention relates to a switching device for switching radio frequency signals. The switching devices comprises at least a first field effect transistor that comprises a first source node, a first gate node and a first drain node, wherein the first gate node is arranged between a first drain region and a first source region on a semiconductor substrate. The switching device comprises at least a second field effect transistor that comprises a second source node, a second gate node and a second drain node, wherein the second gate node is arranged between a second drain region and a second source region on the same semiconductor substrate. The first source region of the first transistor is directly connected to the second drain region of the second transistor to build a common node of the switching device. An input node and an output node of the switching device are directly connected to the common node. The switching device is built by an even number of field effect transistors on the common semiconductor substrate.