RF Switch Gate Drive Circuit for Faster DPDT Switching

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Solution Overview

Problem

RF switch applications face challenges with slow switching times due to high gate capacitance and resistance, leading to significant RC time constant delays, particularly in large switches like DPDT switches.

Innovation Solution

A switching circuit is designed with a transmission gate comprising PMOS and NMOS, coupled with level shifters to apply complementary dynamic pulses, shorting the gate resistor during switching to reduce RC time constants and switching time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If large RF switches are used to achieve double pole double throw functionality, then switching capability is improved, but gate capacitance and resistance increase causing longer switching time

Engineering Contradiction:
Improveswitching capabilityVSAvoidswitching time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The gate control path is segmented into two parallel paths: one through the gate resistor and another through the transmission gate. This segmentation allows the circuit to bypass the resistive path during switching operations, reducing the RC time constant without compromising the overall switching capability of the large RF switch.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A transmission gate is introduced as an intermediary component between the control signal source and the RF switch gate. This transmission gate provides a low-resistance parallel path that mediates the charging/discharging of the gate capacitance, thereby reducing switching time without requiring changes to the main RF switch structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If gate resistance is increased to drive large gate capacitance, then switching capability is maintained, but RC time constant delays increase

Engineering Contradiction:
Improveswitching capabilityVSAvoidswitching speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The high-impedance gate resistor path and the low-impedance transmission gate path are merged in parallel. During normal operation, the gate resistor provides stable biasing, while during switching transitions, the transmission gate provides a low-resistance path. This merging allows both functions to coexist without compromising each other.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The transmission gate is dynamically controlled to be conductive only during switching transitions. The control signals to the transmission gate are synchronized with the RF switch switching events, making the low-resistance path available only when needed for reducing RC time constants, while maintaining stable biasing conditions at other times.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The circuit significantly reduces switching time and turn-on time of RF switches by dynamically shorting the gate resistor, maintaining voltage levels within safe limits to prevent breakdown, enhancing performance and reducing degradation.

Implementation Method 1

A gate capacitance and/or resistance of an RF Switch can create large resistor-capacitor (RC) time constant delays

Methodology Applied
Scientific EffectCapacitance charging/discharging: Capacitance

Data Source

PatentUS12470214B2Radio frequency switching time reducing circuit
Publication Date: 2025.11.11 SKYWORKS SOLUTIONS INC
  • US12470214B2 patent drawing
  • US12470214B2 patent drawing
  • US12470214B2 patent drawing

AI summary

A switching circuit comprises a radio frequency (RF) switch, a gate resistor, a voltage source, a transmission gate, and coupling circuitry configured to couple a gate of the RF switch, a first side of the gate resistor, and the transmission gate at a first node and the voltage source, a second side of the gate resistor, and the transmission gate at a second node.