RF Switch Bias Coupling to Reduce FET Gate-Lag
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Solution Overview
Problem
Radio frequency (RF) switches face a challenge in achieving high switching speeds while maintaining high power handling capability, as the 'gate-lag' phenomenon in field effect transistors (FETs) leads to slow switching speeds due to electron trapping, particularly in type III-V materials like GaAs and GaN FETs.
Innovation Solution
The implementation of a bias coupling circuit that selectively biases the output terminals of FET stacks by coupling gate terminals to output terminals, providing a temporary forward bias voltage to reduce gate-lag without compromising power handling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If stacks of FETs are used to provide high power handling capability, then power handling capability is improved, but switching speed deteriorates due to gate-lag phenomenon
Solution Approach 1:
The patent applies preliminary action by providing a forward bias voltage to the gate terminal before the FET is fully turned on. This preliminary biasing action reduces the formation of surface traps in advance, preventing the gate-lag phenomenon from occurring in the first place, thereby maintaining fast switching speeds while preserving power handling capability through the FET stack configuration
Solution Approach 2:
The patent changes the electrical parameter (gate voltage) dynamically by applying a forward bias voltage during specific phases of operation. This parameter change reduces electron trapping effects and mitigates gate-lag, enabling the FET stack to achieve both high power handling and fast switching performance
2Speed
If forward bias voltage is applied to reduce gate-lag, then switching speed is improved, but power handling capability may be compromised
Solution Approach 1:
The patent applies dynamics by making the gate bias voltage variable rather than fixed. The bias voltage is applied dynamically during specific operational phases (when the FET is turning on) and adjusted according to the switching state. This dynamic control allows the system to reduce gate-lag when needed while maintaining proper power handling characteristics during normal operation
Solution Approach 2:
The patent implements periodic action by applying the forward bias voltage in periodic cycles synchronized with the switching operation. The bias is applied during the transition phase when traps form, then removed during steady-state operation. This periodic application maintains fast switching by preventing trap accumulation without continuously compromising power handling capability
Data Source
AI summary
Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).