RF Switch Gate Resistor Segmentation for Faster Isolation-Safe Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Typical radio frequency switches face a trade-off between switching time and isolation characteristics, where reducing switching time often deteriorates isolation, and maintaining proper resistance values to avoid this deterioration increases switching time, especially in time division duplex communications.

Innovation Solution

The proposed radio frequency switching circuit includes a plurality of switching transistors connected between terminals, a gate resistor circuit with multiple gate resistors connected to each transistor, and a gate buffer circuit with separate buffers connected to each resistor, allowing for improved switching speed without compromising isolation by reducing the size of each component and using parallel transistors to enhance switching speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the resistance value of the gate resistor is reduced to shorten switching time, then switching speed is improved, but isolation characteristics deteriorate

Engineering Contradiction:
Improveswitching delay timeVSAvoidisolation characteristics
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The gate resistor circuit is segmented into multiple gate resistors (first gate resistor and second gate resistor) connected in parallel to the gate of the switching transistor. This segmentation allows each resistor to have a higher individual resistance value while the parallel combination provides lower equivalent resistance, thus reducing switching delay without compromising isolation characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple gate resistors are merged in parallel configuration to achieve the desired equivalent resistance value. The combined effect of multiple high-value resistors in parallel produces a low equivalent resistance that speeds up switching, while each individual resistor maintains its high value for good isolation performance.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If the size of the switching transistor is increased to improve isolation characteristics, then isolation is improved, but switching delay increases

Engineering Contradiction:
Improveisolation characteristicsVSAvoidswitching delay time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention changes the resistance parameter of the gate resistor circuit by using multiple high-value resistors in parallel. This parameter change reduces the equivalent resistance, thereby reducing the RC time constant formed with the transistor's gate capacitance, which speeds up switching without requiring a change in transistor size.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If multiple stacked transistors are used to improve isolation, then isolation characteristics are improved, but the number of components and circuit complexity increase

Engineering Contradiction:
Improveisolation characteristicsVSAvoidnumber of transistors
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate resistor circuit acts as an intermediary element that improves isolation characteristics without requiring multiple stacked transistors. By optimizing the gate resistor configuration (multiple resistors in parallel), the invention achieves good isolation while maintaining a simple single-transistor structure, thus reducing circuit complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10622984B2Radio frequency switching circuit and apparatus with reduced switching response delay
Publication Date: 2020.04.14 SAMSUNG ELECTRO MECHANICS CO LTD
  • US10622984B2 patent drawing
  • US10622984B2 patent drawing
  • US10622984B2 patent drawing

AI summary

A radio frequency switching circuit includes a switching circuit comprising a plurality of switching transistors connected between a first terminal and a second terminal, a gate resistor circuit comprising a plurality of gate resistors, each of the plurality of gate resistors having a first node connected to a respective gate of each of the plurality of switching transistors, and a gate buffer circuit comprising a plurality of gate buffers, each of the plurality of gate buffers being connected to a respective second node of each of the plurality of gate resistors, wherein each of the plurality the gate buffers is configured to provide a first gate signal to the gate of each of the plurality of switching transistors through each of the plurality of gate resistors.