Cross-Coupled RF Switch Circuit for High-Voltage Attenuation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern high-speed wireless communication systems face challenges in designing RF transceivers with embedded Digital Step Attenuators (DSAs) that can tolerate overvoltage and undervoltage conditions, due to the limitations of semiconductor technology nodes with low breakdown voltages and high sensitivity to voltage stress.
Innovation Solution
The proposed solution involves a switch circuit architecture that stacks transistors in series to enhance the maximum tolerable voltage, combined with cross-coupled transistor configurations and voltage clamps to maintain symmetry and linearity, and control circuitry to manage the conductive state of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor gate oxide scaling is reduced to advance semiconductor technology nodes, then device integration and circuit performance are improved, but device breakdown voltage and overvoltage tolerance decrease
Solution Approach 1:
The switch circuit divides the voltage handling task across multiple transistor stacks connected in series. Each stack contains multiple transistors that share the total voltage stress, allowing the use of modern scaled transistors with low individual breakdown voltages while achieving high overall voltage tolerance. The segmentation of voltage handling enables co-integration of DSAs with RF blocks in leading-edge technologies.
Solution Approach 2:
The patent transitions from a single-transistor voltage handling approach to a multi-stack series configuration, adding a dimensional aspect to voltage distribution. By stacking transistors vertically in series chains and connecting multiple chains in series, the solution creates a multi-dimensional voltage distribution architecture that accommodates both scaled device constraints and high voltage requirements.
2Reliability
If multiple transistor stacks are connected in series to increase voltage tolerance, then overvoltage capability is improved, but device complexity increases
Solution Approach 1:
The patent employs asymmetric cross-coupling configurations where transistor stacks of different conductivity types (n-type and p-type) are interconnected in a balanced differential arrangement. This asymmetric design with respect to conductivity types creates symmetry in voltage distribution across the differential signal paths, enabling high voltage tolerance while maintaining circuit balance and linearity.
Solution Approach 2:
The switch circuit architecture serves multiple functions simultaneously: it provides high voltage tolerance through series stacking, maintains differential signal balance through cross-coupling, enables programmable attenuation through control circuitry integration, and achieves low power consumption through efficient transistor switching. This multi-functionality reduces the need for separate circuits for each function.
3Power
If transistor stacks are used to handle high voltage, then power handling capability is improved, but power consumption increases
Solution Approach 1:
The switch circuit operates in periodic switching modes where transistor stacks are alternately activated based on the attenuation control signal. During each switching cycle, only the necessary transistor stacks are conductive, minimizing simultaneous power dissipation across all stacks. This periodic switching enables high power handling capability when needed while maintaining low average power consumption during normal operation.
Solution Approach 2:
The circuit efficiently transitions transistor stacks between conductive and non-conductive states, discarding the high-power conduction state when not needed and recovering to a low-power state. The control circuitry manages the switching of individual transistor stacks, enabling the system to discard power-intensive configurations and recover to energy-efficient states based on signal conditions.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A switch circuit is provided. The switch circuit includes a first node for coupling to a first conductive path and a second node for coupling to a second conductive path. Additionally, the switch circuit includes first and second stacks of transistors arranged between the first and second nodes. A first transistor of the first stack and a first transistor of the second stack are respectively cross-coupled with a second transistor of the second stack and a second transistor of the first stack. The first transistors of the first and the second stack are coupled to the first node. A third transistor of the first stack and a third transistor of the second stack are respectively cross-coupled with a fourth transistor of the second stack and a fourth transistor of the first stack. The fourth transistors of the first and the second stack are coupled to the second node.