RF Switch Circuit With Capacitive Gate Coupling for Low IMD3
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Solution Overview
Problem
Multiport radio-frequency switch circuits, such as SP6T, face challenges with harmonic and intermodulation distortions due to the nonlinear characteristics of FETs, particularly in meeting UMTS requirements for third-order intermodulation distortion (IMD3) without increasing chip size.
Innovation Solution
The implementation of a radio-frequency switch circuit with n-stage through FETs and m-stage shunt FETs, where high-resistance resistors are connected to control signal lines that are capacitively coupled, allowing for effective distortion compensation and reduced IMD3 without increasing the number of stages or chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multistage series connected through FETs and shunt FETs are used to achieve multiport switching, then switching functionality is provided, but harmonic distortion and intermodulation distortion occur due to nonlinear characteristics of FETs
Solution Approach 1:
A capacitor is introduced as an intermediary element connected between the control signal line and the gate of the through FET. This capacitor couples the control signal line to the gate, allowing the control voltage to be applied while providing a specific impedance path that helps reduce the nonlinear effects of the FET, thereby suppressing harmonic and intermodulation distortion while maintaining switching functionality.
Solution Approach 2:
The invention changes the electrical parameters of the control path by adding the capacitor, which modifies the impedance characteristics and voltage distribution at the FET gate. This parameter change optimizes the switching behavior and reduces the nonlinear distortion generated by the FET during switching operations.
2Reliability
If the number of FET stages is increased to improve switching performance, then switching functionality is enhanced, but chip size increases
Solution Approach 1:
The capacitor serves as a compact intermediary element that can be implemented with minimal area on the chip. By using this capacitor to couple the control signal, the invention achieves improved switching performance and distortion reduction without requiring additional FET stages or significant increases in chip area.
3Reliability
If UMTS requirements for third-order intermodulation distortion are met, then system requirements are satisfied, but distortion compensation is difficult without increasing chip size
Solution Approach 1:
The capacitor introduced in the control path provides a compact and effective means to suppress third-order intermodulation distortion. This single capacitive element achieves the required distortion suppression for UMTS systems without requiring complex distortion compensation circuits or increasing the chip size.
Solution Approach 2:
By changing the electrical parameters of the control path through the addition of the capacitor, the invention achieves optimal suppression of third-order intermodulation distortion, meeting UMTS system requirements with minimal impact on chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces third-order intermodulation distortion (IMD3) by approximately 11 dB, improving phase characteristics and maintaining low chip size, effectively addressing the distortion issues in multiport switches.
Implementation Method 1
a radio-frequency leakage prevention resistor connected to a gate of the through FETs
Implementation Method 2
the two control signal lines being capacitively coupled between the resistor and the through FETs
Data Source
AI summary
A radio-frequency switch circuit of the invention includes: n-stage through FETs (field effect transistors) connected in series between the antenna terminal and each of the radio-frequency terminals, where n is a natural number; a radio-frequency leakage prevention resistor connected to a gate of the through FETs; a control signal line commonly connected to the gates of the n-stage through FETs connected to the same radio-frequency terminal; and a resistor connected to each of at least two of the control signal lines and connected to the radio-frequency leakage prevention resistor in series The two control signal lines are capacitively coupled between the resistor and the through FETs.