RF Switch Biasing Topology for Low Standby Current and Die Size
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Solution Overview
Problem
Existing RF switching circuits face challenges in minimizing on-resistance and off-capacitance while maintaining good RF and electrostatic discharge performance, often requiring Negative Voltage Generators (NVGs) or cross-bias capacitors, which can increase controller die size and standby current or degrade RF performance.
Innovation Solution
The proposed solution involves a switching circuit topology using multiple series and shunt Field-Effect Transistors (FETs) configured to create back-to-back diode configurations, allowing for effective switching without the need for NVGs or cross-bias capacitors, by utilizing different gate voltages to manage signal paths and maintain an OFF state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Negative Voltage Generators (NVGs) or cross-bias capacitors are used to minimize off-capacitance and non-linearity, then switching performance is improved, but controller die size and standby current increase
Solution Approach 1:
The patent extracts and eliminates the NVG or cross-bias capacitor components from the switching circuit. By using a novel biasing topology with multiple FETs configured in series and parallel arrangements, the circuit achieves proper biasing without requiring external negative voltage generation or cross-bias capacitors, thereby reducing controller die size while maintaining switching performance
Solution Approach 2:
The switching circuit generates its own bias voltages through the inherent properties of the FET configurations. The series and parallel FET arrangements create the necessary voltage divisions and bias conditions internally, making the circuit self-sufficient and eliminating the need for external NVGs or cross-bias capacitors
2Reliability
If NVGs or cross-bias capacitors are used to minimize off-capacitance, then switching performance is improved, but standby current increases
Solution Approach 1:
The patent removes the energy-consuming NVG or cross-bias capacitor components from the circuit. The new FET-based biasing topology consumes minimal standby current while achieving the same off-capacitance minimization and switching performance through passive voltage division among the FET gates
Solution Approach 2:
The circuit uses the signal voltage itself to generate the necessary bias conditions through the FET configurations, eliminating the need for separate power-consuming bias generation circuits. The FET gates are biased through voltage division from the signal path, making the system energy-efficient
3Reliability
If multiple FETs are configured in series and parallel arrangements, then RF performance and electrostatic discharge performance are maintained, but device complexity increases
Solution Approach 1:
The FETs in the patent serve multiple functions simultaneously: they act as switching elements, voltage dividers, and bias generation components. The same series and parallel FET configurations that provide RF performance also generate the necessary bias voltages and protect against electrostatic discharge, reducing the need for separate dedicated components
Data Source
AI summary
A switching circuit comprises a first series switch coupled to a first output port, the first series switch including a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, a second series switch coupled to a second output port, and coupling circuitry configured to couple a gate of the fifth FET and a gate of the sixth FET to a first node, a source of the fifth FET and a drain of the sixth FET to a second node, a source of the first FET and a drain of the second FET to a third node, a gate of the first FET and a drain of the fifth FET to a fourth node, a gate of the second FET and a source of the sixth FET to a fifth node, the fourth node and the fifth node to a first gate voltage, and the first node to a second gate voltage that is different than the first gate voltage.