High-Frequency Switch Circuit Sequencing for Impedance Stability
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Solution Overview
Problem
Existing high frequency semiconductor integrated circuits face challenges in efficiently managing impedance fluctuations during switching operations, which can lead to performance issues and require complex delay circuitry to mitigate these fluctuations.
Innovation Solution
The proposed high frequency semiconductor integrated circuit employs a configuration with multiple parallel SPDT switches, where the switching operations of the second switching unit are delayed relative to the first, preventing simultaneous OFF states and reducing impedance fluctuations without the need for additional delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching operations are performed in parallel without delay, then switching speed is improved, but impedance fluctuations occur due to simultaneous OFF states
Solution Approach 1:
The patent applies preliminary action by delaying the switching operation of the second switching unit relative to the first switching unit. This sequential switching approach prevents both switches from being in the OFF state simultaneously, thereby avoiding impedance fluctuations while maintaining relatively fast switching performance. The delay is built into the switching control mechanism itself rather than requiring external delay circuits.
2Stability of the object's composition
If delay circuits are added to prevent simultaneous OFF states, then impedance fluctuations are suppressed, but device complexity increases
Solution Approach 1:
The patent merges the delay function directly into the switching unit structure by controlling the second switching unit to operate sequentially after the first switching unit. This integration eliminates the need for separate external delay circuits, thereby suppressing impedance fluctuations while avoiding additional device complexity. The switching control logic itself provides the necessary timing separation.
3Device complexity
If switching units are operated simultaneously, then device complexity is reduced, but harmful impedance fluctuations are generated
Solution Approach 1:
By implementing preliminary action through sequential switching control, the patent ensures that the second switching unit is activated only after the first switching unit has completed its transition. This timing arrangement prevents simultaneous OFF states and the resulting impedance fluctuations, while maintaining a relatively simple switching circuit architecture without requiring complex external delay mechanisms.
Data Source
AI summary
According to one embodiment, a high frequency semiconductor integrated circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, first to fourth switch circuits. In a case where a coupling destination of the first input terminal is switched from the first output terminal to the second output terminal, a third switching operation changing the third switch circuit from an ON state to an OFF state and a fourth switching operation changing the fourth switch circuit from the OFF state to the ON state are finished, after a first switching operation changing the first switch circuit from the ON state to the OFF state and a second switching operation changing the second switch circuit from the OFF state to the ON state are finished.