RF Switching Circuit Biasing With Shunt Path for Low Insertion Loss
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Solution Overview
Problem
Conventional RF/microwave switches, particularly those using depletion-mode GaAs MESFETs or PHEMTs, face issues such as gate current flow leading to increased loss and distortion, lack of complementary device types, and higher die costs, while silicon-based CMOS switches suffer from high insertion loss and poor linearity.
Innovation Solution
A circuit design featuring a first RF switch with a shunt switch and a controller providing control signals to bias the switch between ON and OFF modes, utilizing a silicon CMOS technology with improved substrate insulation to reduce parasitic resistances and enhance isolation, and incorporating inter-gate electrodes to suppress harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If depletion-mode GaAs MESFETs or PHEMTs are used for high-performance RF/microwave switches, then very low Ron and Coff per unit gate width are achieved, but gate current flows when Vgs>0 leading to sharply increased loss and distortion
Solution Approach 1:
The patent changes the operating parameters by using enhancement-mode devices instead of depletion-mode devices, and by implementing specific biasing schemes that keep the gate-source voltage below the threshold for gate current flow while maintaining low insertion loss through optimized device dimensions and bias conditions
Solution Approach 2:
The patent replaces expensive GaAs MESFETs and PHEMTs with silicon-based CMOS devices, which are cheaper and can be manufactured using standard CMOS processes, achieving comparable performance without the gate current issue inherent to Schottky gate devices
2Loss of energy
If depletion-mode GaAs MESFETs or PHEMTs are used for high-performance RF/microwave switches, then very low Ron and Coff per unit gate width are achieved, but the absence of complementary device types increases power consumption and die area
Solution Approach 1:
The patent transitions from depletion-mode devices to enhancement-mode devices, enabling the use of complementary CMOS device pairs (n-channel and p-channel MOSFETs) that can implement push-pull switching and logic functions with lower power consumption and reduced die area compared to single-type GaAs FET implementations
Solution Approach 2:
The patent uses composite CMOS device structures combining n-channel and p-channel MOSFETs in complementary configurations, leveraging the advantages of both device types to achieve low power consumption and compact integration that is not possible with single-type GaAs devices
3Loss of energy
If depletion-mode GaAs MESFETs or PHEMTs are used for high-performance RF/microwave switches, then very low Ron and Coff per unit gate width are achieved, but the die cost per unit area increases due to area-intensive ESD protection structures
Solution Approach 1:
The patent replaces expensive GaAs MESFETs and PHEMTs with silicon-based CMOS devices manufactured using standard CMOS processes, which have mature ESD protection structures that occupy less die area and reduce manufacturing costs while maintaining low insertion loss performance
Solution Approach 2:
The patent changes the device technology platform from GaAs to silicon CMOS, utilizing the inherent advantages of CMOS technology including lower manufacturing costs, smaller ESD protection structure footprints, and compatibility with standard CMOS fabrication processes
4Ease of manufacture
If silicon-based CMOS switches are used, then integration potential and low cost are achieved, but high insertion loss and poor linearity occur
Solution Approach 1:
The patent optimizes the CMOS switch parameters by using enhancement-mode devices with specific W/L ratios, implementing dual-parallel switch configurations, and applying optimized biasing schemes that keep the switches in the deep triode region to minimize on-resistance and insertion loss while maintaining good linearity
Solution Approach 2:
The patent uses composite CMOS device structures combining multiple enhancement-mode MOSFETs in parallel configurations, leveraging the advantages of MOSFET technology to achieve low insertion loss and good linearity that was previously only attainable with GaAs devices
5Ease of manufacture
If silicon-based CMOS switches are used, then integration potential and low cost are achieved, but high insertion loss and poor linearity occur
Solution Approach 1:
The patent changes the device operating parameters by using enhancement-mode MOSFETs with optimized W/L ratios and implementing dual-parallel switch configurations that improve linearity by reducing distortion products, achieving manufacturing precision comparable to GaAs devices at lower cost
Data Source
AI summary
A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complementary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output.