RF Switch Silicide Masking for Parasitic Capacitance Reduction

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Solution Overview

Problem

Semiconductor-based RF switches face a trade-off between insertion loss and isolation, with high power handling requiring large circuit elements that increase capacitance and degrade linearity, necessitating an improvement in the figure of merit and linearity performance.

Innovation Solution

The RF switch design features elongated drain/source diffusion regions, channel regions, and gate structures with a silicide layer covering most diffusion and gate surfaces, except for the resistor regions, which eliminates metal contacts over diffusion regions and reduces parasitic capacitance, thereby enhancing ON state resistance and OFF state capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If large circuit elements are used to achieve low insertion loss and high power handling capability, then power handling capability is improved, but isolation deteriorates due to increased capacitance

Engineering Contradiction:
Improvepower handling capabilityVSAvoidisolation
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent extracts and removes metal contacts from over the diffusion regions, eliminating the parasitic capacitance they create. This extraction allows the circuit elements to be sized for power handling without the isolation-degrading capacitance that would otherwise be introduced by metal contacts.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different qualities to different regions: metal contacts are present at terminal regions for connectivity but deliberately absent from diffusion regions to eliminate parasitic capacitance. This local differentiation allows simultaneous optimization of power handling (through appropriately sized diffusion regions) and isolation (through reduced capacitance).

Inventive Principle:
Principle #3Local quality

2Loss of energy

If large circuit elements are used to achieve low insertion loss, then insertion loss is improved, but linearity deteriorates due to non-linearities in large capacitances

Engineering Contradiction:
Improveinsertion lossVSAvoidlinearity
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

By extracting metal contacts from over the diffusion regions, the patent removes the source of large parasitic capacitances that exhibit non-linear behavior. This extraction preserves the low insertion loss achieved through appropriately sized circuit elements while eliminating the linearity-degrading non-linearities.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If metal contacts are placed over diffusion regions to ensure connectivity, then ease of manufacture is improved, but parasitic capacitance increases degrading isolation

Engineering Contradiction:
Improveease of manufactureVSAvoidisolation
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent extracts metal contacts from over diffusion regions, eliminating the manufacturing simplicity benefit but achieving a much more significant improvement in isolation performance by removing parasitic capacitance. The remaining metal contacts at terminal regions maintain necessary connectivity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by differentiating where metal contacts are present (terminal regions for connectivity) versus absent (diffusion regions to minimize capacitance). This selective application optimizes both manufacturability and electrical performance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10090339B2Radio frequency (RF) switch
Publication Date: 2018.10.02 QORVO US INC
  • US10090339B2 patent drawing
  • US10090339B2 patent drawing
  • US10090339B2 patent drawing

AI summary

Disclosed is a radio frequency (RF) switch that includes a substrate and a plurality of elongated drain/source (D/S) diffusion regions laterally disposed in parallel with one another and separated by a plurality of elongated channel regions. A plurality of elongated D/S resistor regions extends between an adjacent pair of plurality of elongated D/S diffusion regions, and a plurality of elongated gate structures resides over corresponding ones of the elongated channel regions. A silicide layer resides over a majority of at least top surfaces of the plurality of the elongated D/S diffusion regions and the plurality of elongated gate structures, wherein less than a majority of each of the plurality of the elongated D/S resistor regions are covered by the silicide layer.