RF FET Switch Stack Gate Resistor Bypass for Faster Switching
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Solution Overview
Problem
Existing RF FET switch stacks face challenges in reducing switching time due to the presence of gate resistors, which hinder efficient transition between ON and OFF states.
Innovation Solution
A dynamic gate control block is introduced, featuring a series combination of nMOS and pMOS transistors that bypass common gate resistors during transition states, allowing both transistors to be in an ON state during transition periods and maintaining high impedance during steady states, thereby reducing switching time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate resistors are used in the FET switch stack, then the switching devices can be controlled and protected, but the switching time increases and transition speed decreases
Solution Approach 1:
The patent implements a dynamic gate control mechanism where the gate resistance is not fixed but changes during operation. A bypass transistor is introduced that can dynamically short the gate resistor during transition periods, while the resistor remains active during steady states. This dynamic switching of the resistance state allows the system to achieve fast switching during transitions while maintaining stable control during steady operation.
Solution Approach 2:
The bypass transistor is activated in advance during the transition period before the FET reaches its final steady state. By preparing the low-resistance path beforehand, the gate voltage can change rapidly during the critical transition phase, reducing the overall switching time without compromising the protective function of the gate resistor during normal operation.
2Reliability
If gate resistors are present in the circuit, then the FET switches can be reliably controlled, but the charging time of the main switch increases
Solution Approach 1:
The gate control circuit transitions from a static resistance configuration to a dynamic one by introducing a bypass transistor. During the charging phase, the bypass transistor conducts and effectively removes the gate resistor from the circuit, allowing rapid charging of the gate capacitance. Once charging is complete and the FET reaches its steady state, the bypass transistor turns off and the gate resistor resumes its protective function, ensuring reliable control while minimizing charging time.
3Device complexity
If common gate resistors are used for multiple FET switches, then the circuit complexity is reduced, but the transition speed of individual switches is limited
Solution Approach 1:
The patent segments the gate control function by introducing individual bypass transistors for each FET switch in the stack, even though they share common gate resistors. This segmentation allows each FET to have its own dynamic control path that can be independently activated during transitions, enabling faster individual switching without requiring separate gate resistors for each device. The common gate resistors maintain circuit simplicity while the individual bypass transistors provide the speed enhancement.
Data Source
AI summary
A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.