Drain-Source Bypass Circuitry in RF FET Switch Stacks
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Solution Overview
Problem
Existing RF circuits using FET switch stacks with larger gate resistors experience slow switching speeds and snapback issues when transitioning from the ON to the OFF state, failing to meet stringent design requirements.
Innovation Solution
Implementing drain-source bypass switches across the drain-source resistors in the FET switch stack to bypass these resistors during the transition, reducing the RC time constant and preventing snapback effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger gate resistors are used in FET switch stacks, then linearity and insertion loss are improved, but switching speed deteriorates
Solution Approach 1:
The patent implements bypass switches that dynamically change the circuit configuration during switching transitions. These bypass switches temporarily short-circuit the gate resistors during transitions, reducing the effective resistance and RC time constant, thereby improving switching speed without permanently removing the resistors that provide linearity and insertion loss benefits during steady-state operation.
2Speed
If gate bypass switches are implemented to improve transition speed, then switching speed is improved, but snapback effects occur during transition
Solution Approach 1:
The patent introduces drain-source bypass switches as intermediary elements that provide an alternative current path during transitions. These switches bypass the drain-source resistors, preventing the discharge of gate capacitance through the resistors that causes snapback effects, while still allowing the gate bypass switches to function in improving transition speed.
3Reliability
If drain-source resistors are present in charging paths, then linearity is improved, but switching speed deteriorates due to RC time constant
Solution Approach 1:
The patent implements drain-source bypass switches that dynamically alter the circuit topology during switching transitions. These switches temporarily remove the drain-source resistors from the charging paths by providing parallel low-resistance paths, reducing the RC time constant and improving switching speed while preserving the resistors for steady-state linearity performance.
4Speed
If bypass switches are used during transition, then switching speed is improved, but device complexity increases
Solution Approach 1:
The patent designs the bypass switches to serve multiple functions: gate bypass switches improve transition speed by reducing gate RC time constants, while drain-source bypass switches prevent snapback effects and further reduce charging path resistance. This multi-functional approach consolidates several benefits into a unified circuit architecture, offsetting the added complexity with enhanced overall performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves switching speed and ensures a stable OFF state without snapback, meeting the stringent requirements of RF circuits.
Implementation Method 1
reducing the RC time constant imposed by a combination of each drain-source resistor with corresponding device gate capacitor
Implementation Method 2
preventing snapback effects
Data Source
AI summary
Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.