RF Switch Transistor Stack With Symmetric Bias Network
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Solution Overview
Problem
Existing RF switches face challenges in balancing power losses and switching times, particularly in antenna switches where high linearity is required to prevent spurious and harmonic signals from interfering with the intended signal, and the number of transistors in the stack affects these parameters.
Innovation Solution
A switch comprising a stack of transistors with a symmetric bias network, where every two successive transistors form a pair, and the bias network includes connections that ensure equal resistance profiles across all transistors, reducing power losses and enhancing switching speed while rejecting even harmonics through capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transistors are arranged in series to form a stack for RF switching, then the isolation and switching control are improved, but the power losses increase and switching time is affected
Solution Approach 1:
The transistor stack is divided into multiple individual transistor stages, each with its own bias network. This segmentation allows independent optimization of each transistor's contribution to isolation versus power loss, enabling the overall stack to achieve high isolation while minimizing cumulative power losses through balanced design of individual stages.
2Reliability
If multiple transistors are arranged in series to form a stack for RF switching, then the isolation and switching control are improved, but the switching time is affected
Solution Approach 1:
The bias network incorporates dynamic control elements that can rapidly adjust the bias conditions of each transistor in the stack. This dynamic capability enables fast switching transitions while maintaining the high isolation benefits of the multi-transistor series configuration, resolving the contradiction between isolation and switching speed.
3Reliability
If a high number of transistors are used in the stack to improve linearity, then even harmonic rejection is improved, but the power losses and device complexity increase
Solution Approach 1:
The transistor stack is segmented into multiple stages with symmetric bias networks, where each stage contributes equally to harmonic rejection. This segmentation achieves the required linearity and even harmonic rejection through the cumulative effect of multiple balanced stages, while the modular structure manages device complexity by repeating standardized units rather than requiring a monolithic complex design.
Solution Approach 2:
The bias network employs asymmetric resistor configurations in certain stages to create differential voltage swings that cancel even harmonics. This controlled asymmetry in the bias distribution across the symmetric transistor stack enables superior even harmonic rejection while maintaining overall device manageability through the regular repeating structure.
Data Source
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AI summary
Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.