RF Switch Transistor Stacking for High Power With Lower Insertion Loss
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Solution Overview
Problem
Existing radio frequency switch circuits face challenges in achieving high-power mode capabilities due to uneven voltage swing distribution in transistor stacks, leading to reduced power output and increased insertion loss.
Innovation Solution
The proposed radio frequency switch circuit employs a series connection of switch transistor units, each stage comprising a first, second, and third transistor, along with specific resistor and capacitor configurations to ensure balanced voltage distribution and reduced insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a plurality of switch transistors are connected in series to improve power output capability, then the power output capability is improved, but the insertion loss increases and the chip area increases
Solution Approach 1:
The patent divides the switch transistor into multiple stages (first stage, second stage, third stage, etc.), where each stage includes a first transistor, second transistor, and third transistor connected in a specific configuration. This segmentation allows the voltage swing to be distributed across multiple stages, reducing the voltage swing burden on each individual transistor and thereby reducing insertion loss while maintaining high power output capability.
Solution Approach 2:
The patent applies different connection configurations to different stages of the switch transistor. Specifically, the first transistor of each stage has its gate connected to a gate bias resistor, its drain connected to the source of the first transistor in the previous stage, and its source connected to the drain of the first transistor in the next stage. This local quality differentiation optimizes the voltage distribution across each stage, reducing overall insertion loss.
2Power
If a plurality of switch transistors are connected in series to improve power output capability, then the power output capability is improved, but the chip area occupied increases
Solution Approach 1:
The patent merges multiple transistors into compact stages, where each stage includes a first transistor, second transistor, and third transistor with shared connections. The gate of the second transistor is connected to the source of the first transistor, and the gate of the third transistor is connected to the drain of the first transistor. This merging approach reduces the total chip area compared to using separate transistors for each function.
Solution Approach 2:
The patent implements a nested structure where the second and third transistors are effectively nested within the stage structure defined by the first transistor. The body of the first transistor is connected to both the source and drain of subsequent transistors, creating a compact nested arrangement that minimizes chip area while maintaining the required number of transistor stages for high power output.
3Power
If the quantity of stacked switch transistors is increased to improve power output capability, then the power output capability is improved, but the insertion loss increases
Solution Approach 1:
The patent introduces dynamic biasing through gate bias resistors connected to the gates of the first transistors in each stage. This dynamic control allows the voltage swing to be optimally distributed across the stacked transistors, preventing any single transistor from experiencing excessive voltage stress that would increase insertion loss. The gate bias resistors enable adaptive voltage distribution as the number of stacked transistors increases.
Solution Approach 2:
The patent uses gate bias resistors as intermediary elements between the gate bias voltage and the gates of the first transistors. These resistors act as mediators that control the voltage distribution across the stacked transistors, ensuring that the voltage swing is evenly distributed and preventing excessive voltage drops that would increase insertion loss in high-power configurations.
Data Source
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AI summary
Disclosed are a radio-frequency switch circuit supporting a high-power mode, a chip, and an electronic device. The radio-frequency switch circuit is formed by connecting multiple stages of switch transistor units in series. In each stage of switch transistor unit, a gate of a first transistor is connected to a gate bias resistor, and the other end of the gate bias resistor is connected to a gate bias voltage; a drain of the first transistor is connected to a source of a first transistor in the previous stage of switch transistor unit, and a source of the first transistor is connected to a drain of a first transistor in the next stage of switch transistor unit; two ends of a path resistor are respectively connected to the drain and source of the first transistor, and a body of the first transistor is connected to a source of a second transistor and a source of a third transistor, respectively; a gate of the second transistor is connected to the source of the first transistor, and a gate of the third transistor is connected to the drain of the first transistor. The radio-frequency switch circuit provided by the present invention has a significantly improved power output capability.