RF Switch FET Stack Voltage Equalization for Breakdown Prevention
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Solution Overview
Problem
RF switches with FET stacks face challenges in maintaining high power handling capability while ensuring fast switching speed, as unequal source-drain voltages across FETs can lead to breakdown or failure, necessitating improved voltage equalization across FETs in series-coupled stacks.
Innovation Solution
The implementation of compensation circuits that electrically couple the transistor body of one FET to the gate of another within the FET stack, using impedances such as capacitors or RC series circuits, to equalize source-drain voltages and improve voltage handling capacity while maintaining high speed switching by altering FET dimensions for parallel stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If series-coupled FET stacks are used to provide high power handling capability, then voltage handling capacity is improved, but unequal source-drain voltages across FETs can lead to breakdown or failure
Solution Approach 1:
The patent applies equipotentiality by coupling transistor bodies to gates through compensation circuits (capacitors or RC networks) to equalize the source-drain voltages across all FETs in the series stack. This ensures that each FET experiences nearly equal voltage stress, preventing any single device from exceeding its breakdown voltage while maintaining the high voltage handling capability of the series configuration.
2Strength
If compensation circuits are added to equalize voltages across FETs, then voltage handling capacity is improved, but device complexity increases
Solution Approach 1:
The patent uses compensation circuits as intermediary elements between transistor bodies and gates. These circuits (comprising capacitors or RC networks) act as mediators that sense voltage imbalances and provide compensating signals to equalize the voltage distribution across the FET stack, thereby achieving voltage equalization without requiring fundamental changes to the switch architecture.
3Speed
If FET dimensions are altered for parallel stacks to maintain high speed switching, then switching speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter changes by adjusting FET physical dimensions (such as channel width or length) when configuring parallel stacks to optimize switching speed. By carefully controlling these dimensional parameters, the design achieves faster switching performance while the compensation circuits simultaneously ensure uniform voltage distribution, thereby managing the trade-off between speed optimization and manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively equalizes voltages across FETs, enhancing the power handling capability of RF switches while maintaining high speed switching by compensating for parasitic leakage currents and reducing voltage variations, thereby preventing premature breakdown.
Implementation Method 1
compensating for parasitic leakage currents and reducing voltage variations
Data Source
AI summary
Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.