RF Switch Wiring Layout Optimization for RonCoff Reduction
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Solution Overview
Problem
Current chip structures with high frequency switches face challenges in improving figures of merit such as on-resistance (Ron) and off-capacitance (Coff) due to the conventional parallel alignment of wiring in BEOL interconnect structures, which affects the routing of high frequency signals in mobile communication devices.
Innovation Solution
The chip structure incorporates a wiring layout where wires are aligned non-parallel to the gate electrodes, increasing spacing and reducing wiring capacitance, thereby enhancing the figures of merit by engineering the on-resistance and off-capacitance through modified BEOL interconnect structure fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires are aligned parallel to gate electrodes in conventional BEOL interconnect structures, then routing simplicity is maintained, but wiring capacitance increases and figures of merit deteriorate
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the wiring grid with the transistor gate electrodes. Specifically, wires in different metallization levels are shifted relative to each other and to the gate electrodes, creating an asymmetric layout that reduces parasitic capacitance between wires and gates, thereby improving switch on-resistance and off-capacitance figures of merit.
Solution Approach 2:
The patent utilizes the vertical dimension by employing multiple metallization levels (M1, M2, M3, etc.) with progressive horizontal shifts. This multi-dimensional approach allows wires to be routed effectively while maintaining increased spacing from gate electrodes, reducing capacitance without compromising routing connectivity.
2Reliability
If wiring capacitance is reduced by increasing spacing, then off-capacitance improves, but routing efficiency may deteriorate
Solution Approach 1:
The patent resolves this contradiction by utilizing multiple metallization levels to provide alternative routing paths. When wires are spaced apart to reduce capacitance, the multi-level structure enables signals to route through different vertical layers, maintaining routing efficiency while preserving the capacitance reduction benefits.
Solution Approach 2:
The routing path is segmented across multiple metallization levels rather than confined to a single plane. This segmentation allows the wire to achieve both increased spacing from gate electrodes (improving Coff) and effective signal routing (maintaining productivity) by transitioning between different vertical layers.
Data Source
AI summary
Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.