RF Circuit Time Domain Isolation for Digital Noise Reduction
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Solution Overview
Problem
Conventional wireless communication apparatus face interference challenges due to the overlap in time between RF reception or transmission activities and signal processing tasks, which affects performance and noise levels.
Innovation Solution
Implementing a time domain isolation technique that separates RF reception or transmission activities from signal processing tasks by using a scheduler to schedule channel equalization and decode tasks during specific time slots, allowing the digital processing circuit to be inactive during RF timeslots and active during signal processing timeslots, thereby reducing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signal processing tasks are scheduled to occur immediately following or during RF signal reception, then processing efficiency is improved, but digital noise and spurious signals increase due to interference between RF and digital circuits
Solution Approach 1:
The patent segments the operation timeline into distinct RF reception time slots and digital processing time slots. The scheduler divides tasks such that RF reception and digital signal processing occur in separate, non-overlapping time periods, preventing interference while maintaining processing efficiency.
Solution Approach 2:
The patent implements periodic alternation between RF reception modes and digital processing modes. The scheduler periodically switches the digital processing circuit between inactive states during RF reception and active states during processing time slots, creating a rhythmic pattern that eliminates interference while ensuring timely processing.
2Productivity
If RF reception and digital processing occur simultaneously, then overall system throughput is improved, but performance deteriorates due to mutual interference between RF and digital circuits
Solution Approach 1:
The patent segments the operational timeline to separate RF reception activities from digital processing activities into distinct time slots. This segmentation ensures that high-performance RF reception and digital signal processing do not occur simultaneously, eliminating mutual interference while the scheduler maintains high system throughput through efficient task allocation.
Solution Approach 2:
The scheduler performs preliminary scheduling of digital processing tasks to be executed in advance during dedicated processing time slots, before the next RF reception cycle begins. This preliminary action ensures that processing is completed without interfering with upcoming RF reception, maintaining both throughput and performance.
Data Source
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AI summary
A communication apparatus includes a radio frequency (RF) circuit configured to operate on an RF signal, and a digital processing circuit that is coupled to the RF circuit. The digital processing circuit may operate in association with the RF circuit according to a time domain isolation technique. In addition, the digital processing circuit includes a scheduler that may schedule a channel equalization task for each of one or more respective receive time slots. The scheduler may also schedule a decode task to obtain slot allocation information for each of the one or more respective receive time slots.