RF Transceiver with Integrated ADC, DAC, and SerDes
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Solution Overview
Problem
The integration of growing quantities of receive and transmit paths in wireless communications devices results in large chip areas and high power consumption due to numerous hardware connections between radio frequency and baseband chips, particularly in technologies like MIMO and carrier aggregation.
Innovation Solution
A wireless transceiver apparatus utilizing a digital interface architecture with integrated analog to digital converters, digital to analog converters, and serializer/deserializers in the radio frequency chip, coupled with a common clock phase-locked loop, reduces hardware connections and power consumption by enabling serial digital communication between the radio frequency and baseband chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple input multiple output (MIMO) and carrier aggregation (CA) technologies are integrated, then communication capability is improved, but chip area and power consumption increase due to large quantity of hardware connections
Solution Approach 1:
The patent integrates the ADC, DAC, and SerDes into a single RFIC, merging multiple previously separate components into one unified chip. This consolidation reduces the number of external connections and inter-chip interfaces required for MIMO and CA technologies, thereby reducing chip area while maintaining enhanced communication capability.
Solution Approach 2:
The RFIC is designed to perform multiple functions including ADC, DAC, SerDes, and radio frequency processing within a single integrated circuit. This multi-functional design allows the chip to support MIMO and carrier aggregation technologies without requiring separate dedicated components, thus reducing overall chip area and power consumption.
2Adaptability or versatility
If multiple input multiple output (MIMO) and carrier aggregation (CA) technologies are integrated, then communication capability is improved, but power consumption increases due to large quantity of hardware connections
Solution Approach 1:
By merging ADC, DAC, and SerDes into one RFIC, the patent eliminates multiple inter-chip connections and reduces the power consumed by external signal transmission. The integrated design allows for more efficient power management and reduces overall power consumption while supporting advanced communication capabilities.
Solution Approach 2:
The patent extracts the ADC, DAC, and SerDes functions from the baseband chip and relocates them into the RFIC. This extraction reduces the power consumption associated with external analog interfaces and multiple parallel connections, thereby lowering overall power consumption while maintaining communication capability.
3Device complexity
If analog interface architecture is used between radio frequency chip and baseband chip, then signal processing is simplified, but large quantity of hardware connections increase chip area
Solution Approach 1:
The patent combines ADC, DAC, and SerDes into the RFIC, merging the analog interface functions with digital processing capabilities in a single chip. This integration eliminates the need for multiple external analog connections while maintaining simplified signal processing, thereby reducing chip area without increasing complexity.
4Device complexity
If analog interface architecture is used between radio frequency chip and baseband chip, then signal processing is simplified, but power consumption increases
Solution Approach 1:
By merging ADC, DAC, and SerDes into the RFIC, the patent creates an integrated design that simplifies signal processing while reducing power consumption. The unified architecture eliminates redundant power consumption from external analog interfaces and multiple parallel connections, achieving both simplified processing and lower power usage.
Data Source
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AI summary
Embodiments of this application disclose a wireless transceiver apparatus. The apparatus includes a radio frequency receiver, a radio frequency transmitter, a first serializer/deserializer, and a common clock phase-locked loop. The radio frequency receiver, the radio frequency transmitter, the first serializer/deserializer, and the common clock phase-locked loop are integrated in a radio frequency chip. The radio frequency receiver includes a down converter and an analog to digital converter. The radio frequency transmitter includes an up converter and a digital to analog converter. The first serializer/deserializer is configured to provide a serial digital interface with a baseband chip for the radio frequency chip. Coupled to the analog to digital converter, the digital to analog converter, and the first serializer/deserializer separately, the common clock phase-locked loop is configured to provide a clock signal for the analog to digital converter, the digital to analog converter, and the first serializer/deserializer. The wireless transceiver apparatus can reduce an area and/or power consumption of a chip.