RF Transceiver Loopback Testing via Shared Modulated PLL
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Solution Overview
Problem
The existing methods for testing constant envelope RF transceivers require expensive equipment and serial testing, limiting parallel testing of multiple die and increasing test costs and time, especially when integrated with a processor.
Innovation Solution
A method and integrated circuit design that utilize a shared phase locked loop (PLL) for simultaneous time-division receive and transmit operations, enabling loopback testing without expensive equipment, allowing for parallel testing of multiple transceivers and reducing test time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If expensive test equipment is used for RF transceiver testing, then testing accuracy and reliability are improved, but test cost increases
Solution Approach 1:
The RF transceiver tests itself by generating test signals internally through its own transmitter and analyzing the loopback signals through its own receiver, eliminating the need for expensive external test equipment. The transceiver uses its integrated PLL and modulator to generate test signals and processes the received signals to determine pass/fail status
Solution Approach 2:
The test method utilizes the existing transmitter and receiver components for dual purposes: normal communication operations and self-testing operations. The same hardware blocks (transmitter, receiver, PLL, modulator) serve both functional operations and test operations, eliminating the need for separate dedicated test equipment
2Device complexity
If serial testing is used for transceiver with single PLL, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The transmitter and receiver operate in time-division periodic cycles, with each completing full operational cycles including test signal generation and loopback signal reception. This periodic operation allows both transmitter and receiver to be fully functional during testing while maintaining the single PLL architecture
Solution Approach 2:
The system dynamically switches between different operational modes (transmit mode, receive mode, test mode) within the same hardware configuration. The single PLL is dynamically allocated to different functions at different time intervals, enabling parallel testing capability without requiring duplicate hardware
3Device complexity
If serial testing is used for MCU and transceiver, then device complexity is reduced, but loss of time increases
Solution Approach 1:
The testing of the MCU and RF transceiver is merged into a single parallel testing operation. Both the MCU processor core and the RF transceiver are tested simultaneously using the same test infrastructure, with the transceiver providing self-test capability and the MCU being tested through its interaction with the transceiver and external test equipment
Solution Approach 2:
The RF transceiver acts as an intermediary that enables parallel testing of the MCU. The transceiver's self-test capability allows it to be tested independently while simultaneously serving as a test platform for the MCU, effectively mediating between the two testing requirements and enabling concurrent operation
Data Source
AI summary
An integrated circuit includes a receiver portion, a transmitter portion, and a modulated phase locked loop. The receiver portion is for receiving a radio frequency (RF) signal at a receiver input of the receiver portion. The transmitter portion is for transmitting an RF signal at a transmitter output of the transmitter portion. The modulated phase locked loop (PLL) is shared between the receiver portion and the transmitter portion. The transmitter output and receiver input are coupled together in a loopback configuration during a test mode. The transmitter portion and the receiver portion are enabled concurrently while a modulated PLL signal is provided to the receiver portion from the transmitter portion via the loopback configuration.