RF Transceiver Digital Spur Reduction via Clock Frequency Shifting

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Solution Overview

Problem

In RF transceivers with mixed digital and analogue circuitry, digital spurs can interfere with analogue components, leading to poor signal-to-noise ratios due to the amplification of spurious spectral lines, which existing isolation techniques may not adequately address, especially in CMOS technology where area constraints are significant.

Innovation Solution

The solution involves generating a local oscillator signal and a digital clock signal such that any spurs from digital components are shifted outside the intermediate frequency band, ensuring they are either mixed to DC or filtered out, using techniques like making the digital clock signal a sub-harmonic of the local oscillator signal or adjusting the reference signal frequency to keep harmonics outside the selected band.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If digital components are placed on the same die as analogue components to reduce area, then area is reduced, but digital spurs interfere with analogue components degrading signal-to-noise ratio

Engineering Contradiction:
Improveintegrated circuit areaVSAvoiddigital spur interference
Core Design Contradiction:
Area of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent segments the frequency spectrum by carefully selecting the digital clock frequency and its harmonics to fall outside the analogue signal bandwidth. This allows digital and analogue components to coexist on the same die without significant interference, as the digital spurs are spectrally separated from the analogue signal band.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the digital clock frequency parameter to a sub-harmonic of the centre frequency (fc/N) rather than using conventional clock frequencies. This parameter change ensures that digital spurs occur at frequencies that do not overlap with the analogue signal band, resolving the interference problem while maintaining area efficiency.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If isolation techniques such as separate power supplies or deep-N well isolation are used to reduce digital spur interference, then digital spur interference is reduced, but device complexity and area increase

Engineering Contradiction:
Improvedigital spur interferenceVSAvoidisolation technique complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts the harmful digital spurs from the analogue signal band by selecting a digital clock frequency where its harmonics fall outside the signal bandwidth. This eliminates the need for complex isolation techniques, as the spurs are naturally separated in the frequency domain rather than requiring physical or electrical isolation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses frequency domain separation as an intermediary mechanism to prevent digital-spur-induced errors. By ensuring digital spurs fall outside the analogue signal band, the frequency spectrum acts as a mediator that prevents interference without requiring additional isolation circuitry.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If the digital clock frequency is increased to improve digital performance, then digital performance is improved, but digital spurs fall into the analogue signal band degrading signal quality

Engineering Contradiction:
Improvedigital clock frequencyVSAvoidspur frequency overlap
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

Instead of increasing the digital clock frequency to improve performance, the patent inverts the approach by using a sub-harmonic frequency (fc/N) that is lower than conventional clocks. This inversion ensures that even at lower frequencies, the digital spurs fall outside the analogue signal band, maintaining signal quality while still achieving adequate digital performance.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the digital clock frequency parameter to a specific sub-harmonic of the centre frequency (fc/N) rather than using higher frequencies. This parameter change resolves the contradiction by positioning digital spurs in frequency regions that do not overlap with the analogue signal band.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes the impact of digital spurs on the analogue components, improving the signal-to-noise ratio by ensuring spurs are kept outside the intermediate frequency band, thereby enhancing the performance of the RF transceiver.

Implementation Method 1

a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal

Methodology Applied
Scientific EffectFrequency mixing: Heterodyne

Data Source

PatentEP2383914B1RF digital spur reduction
Publication Date: 2015.01.28 NXP BV
  • EP2383914B1 patent drawingFigure 1~2
  • EP2383914B1 patent drawingFigure 3~4
  • EP2383914B1 patent drawingFigure 5~6

AI summary

The disclosure relates to digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit (200) having digital components (209) and analogue components (202, 203, 204), the circuit comprising: a radiofrequency signal receiver comprising a local oscillator signal generator (205) configured to provide a local oscillator signal at a frequency fLO and a mixer (203) configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator (208) configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.