Low Parasitic Capacitance RF Transistors Using Insulating Handle Wafer
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Solution Overview
Problem
Conventional CMOS SOI FETs suffer from parasitic capacitive coupling, thermal barriers, and voltage breakdown issues due to the buried oxide layer, leading to increased leakage current, reduced breakdown voltage, crosstalk, and non-linearity, particularly in RF transistors.
Innovation Solution
The use of an insulating low dielectric constant handle wafer in Single Layer Transfer (SLT) or Double Layer Transfer (DLT) fabrication techniques replaces the silicon substrate, reducing parasitic capacitance and improving thermal conductivity by positioning the handle wafer above the metal interconnect layers or entirely replacing the silicon substrate, thereby mitigating parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a buried oxide layer is used in SOI FETs, then fabrication is simplified and certain parasitic effects are avoided, but parasitic capacitive coupling to the substrate increases, causing increased leakage current, lower breakdown voltage, crosstalk, and linearity degradation
Solution Approach 1:
The patent extracts and removes the silicon substrate from the SOI FET structure, eliminating the source of parasitic capacitive coupling. By suspending the semiconductor layer above a cavity or using a handle wafer that is subsequently removed, the buried oxide layer is decoupled from the conductive substrate, thereby removing the harmful capacitive coupling effect while preserving the fabrication benefits of SOI technology.
Solution Approach 2:
The patent introduces air cavities or void spaces beneath the buried oxide layer to replace the solid silicon substrate. These porous/empty spaces eliminate the conductive path and capacitive coupling to the substrate, while still allowing the buried oxide layer to provide its intended isolation and fabrication support functions during manufacturing.
2Reliability
If a buried oxide layer is used in SOI FETs, then device isolation is improved, but thermal conduction is blocked, creating a thermal barrier that increases junction temperature
Solution Approach 1:
The patent segments the thermal management path by introducing lateral thermal conduction paths through the handle wafer or substrate regions adjacent to the active device. While the buried oxide layer remains as an thermal barrier directly beneath the channel, heat can escape through the sides via the handle wafer, creating multiple thermal egress routes that reduce the overall thermal resistance and junction temperature.
Solution Approach 2:
The patent transitions from vertical-only heat dissipation (through the buried oxide) to multi-dimensional heat management by enabling lateral heat flow through the handle wafer and substrate regions. This adds horizontal thermal conduction paths, effectively creating a three-dimensional thermal management architecture that reduces thermal bottlenecks.
3Strength
If a silicon substrate is used in conventional SLT transistors, then mechanical support is provided, but parasitic capacitance is introduced, causing insertion loss, isolation degradation, and non-linearity in RF transistors
Solution Approach 1:
The patent uses a disposable handle wafer that provides temporary mechanical support during fabrication and processing, then removes it to eliminate parasitic capacitance. The handle wafer serves its structural purpose only during manufacturing, after which it is released and discarded, leaving the active device suspended without the harmful capacitive coupling to a permanent substrate.
Solution Approach 2:
The patent changes the dielectric constant parameter of the material beneath the active device from that of silicon (high dielectric constant, ~11.7) to air or vacuum (dielectric constant = 1), thereby dramatically reducing parasitic capacitance. This parameter change is achieved by removing the silicon substrate or filling the space with low-dielectric materials.
Data Source
AI summary
Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.