Segmented RF Transmitter Phase Mapping for Spectral Purity

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Solution Overview

Problem

Existing digital transmitters face challenges in achieving high efficiency and spectral purity, especially at higher power levels due to irregularities in RF output current distribution and switch bank layout, which are difficult to correct through signal processing.

Innovation Solution

A digitally controlled segmented RF power transmitter using a sign-bit phase mapper that generates 50% duty-cycle clock signals, distributed through a clock tree, to produce low-duty-cycle upconverting signals for the DTX segments, reducing clock line coupling and improving LO signal handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If digital transmitters use higher power levels with traditional switch bank layouts, then output power increases, but RF output current distribution becomes irregular and spectral purity degrades

Engineering Contradiction:
Improveoutput powerVSAvoidspectral purity
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The transmitter output stage is divided into multiple independently controllable segments or unit cells. Each segment can be activated or deactivated based on the required power level, allowing precise control of RF output current distribution. This segmentation enables linear CWD to RF output signal transfer by ensuring that only segments with proper current distribution characteristics are activated at each power level.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If traditional analogue RF frontend is used, then design is simpler, but power consumption increases significantly in low traffic scenarios

Engineering Contradiction:
Improvefrontend design simplicityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The digital transmitter uses periodic clock signals with 50% duty cycle to drive the segmented output stage. By using periodic activation of segments rather than continuous analogue operation, the system achieves significant power savings in low traffic scenarios while maintaining signal integrity through digital control mechanisms.

Inventive Principle:
Principle #19Periodic action

3Reliability

If 50% duty-cycle clock signals are distributed through clock tree, then LO signal handling is improved, but clock line coupling effects occur

Engineering Contradiction:
ImproveLO signal handlingVSAvoidclock line coupling
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The clock distribution system is segmented to provide clock signals to different groups of output segments. By dividing the clock tree into multiple independent distribution paths, the coupling effects between clock lines are reduced while maintaining robust LO signal handling at each segment. This segmentation allows proper phase relationships to be maintained without suffering from cumulative coupling effects.

Inventive Principle:
Principle #1Segmentation

4Manufacturing precision

If sign-bit phase mapper generates low-duty-cycle upconverting signals, then spectral purity enhances, but duty-cycle distortion becomes more sensitive

Engineering Contradiction:
Improvespectral purityVSAvoidduty-cycle distortion sensitivity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The sign-bit phase mapper performs preliminary phase adjustment on the 50% duty-cycle clock signals before they reach the output segments. By pre-establishing the correct phase relationships and duty cycles at the clock generation stage, the system achieves spectral purity through low-duty-cycle upconverting signals while maintaining robustness against duty-cycle distortion through the inherent symmetry of the 50% duty-cycle reference signals.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12562762B2Digital transmitter featuring a 50%-LO signed phase mapper
Publication Date: 2026.02.24 TECH UNIV DELFT
  • US12562762B2 patent drawing
  • US12562762B2 patent drawing
  • US12562762B2 patent drawing

AI summary

Provided herein is a digitally controlled segmented RF power transmitter with a digital processing part and an RF power amplification part having a plurality of segments. The digital processing part has a clock generation block arranged to generate n equi-phased clock signals with a 50% duty-cycle (fLO,x_50%, Cx), and a sign-bit phase mapper unit arranged to receive the n equi-phased clock signals (fLO,x_50%; Cx), and sign bits (SignI, SignQ), and to output a set of m, m≤n, phase mapped clock signals with a 50% duty-cycle (CLKy,50%; Cy) using a predetermined phase swapping scheme. Each of the plurality of segments includes logic circuitry receiving the set of m phase-mapped clock signals with a 50% duty-cycle (CLKy,50%; Cy), and arranged to provide the respective segment driving signal with a duty-cycle z of less than 50%.