RF Up-Conversion with Non-Overlapping Clocked Baseband Sampling
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Solution Overview
Problem
Conventional digital polar transmitters for wireless communication systems require high clock rates, consuming large area and power, and degrade Error Vector Magnitude (EVM) with increasing signal bandwidth, while I/Q RF DACs are area-intensive and power-inefficient, posing a challenge for low-cost, low-power, and high-bandwidth digital transmission.
Innovation Solution
A digital signal up-converting apparatus comprising a clock generating circuit, an adjusting circuit, and a sampling circuit that generates non-overlapping clock signals to sample and combine digital output signals, reducing power consumption and area while maintaining signal integrity by using a switch amplifier to up-convert baseband data into RF signals without simultaneous differential device activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a digital polar transmitter is used to transmit RF signal, then area saving and power efficiency are achieved, but large area and digital power are consumed due to high clock rate CORDIC
Solution Approach 1:
The patent segments the baseband signal processing into multiple parallel channels (I and Q channels), each operating at lower clock rates. The baseband circuit generates separate I and Q digital output signals that are processed independently and then combined, avoiding the need for a single high-clock-rate CORDIC processor and reducing overall power consumption and area.
Solution Approach 2:
The patent employs periodic sampling of the baseband I and Q signals using non-overlapping clock signals. The sampling circuit samples the digital output signals at specific intervals determined by the clock periods, enabling reconstruction of the RF signal through periodic modulation without requiring continuous high-rate processing.
2Speed
If signal bandwidth increases in digital polar transmitter, then bandwidth is improved, but EVM degrades due to truncation mechanism
Solution Approach 1:
The patent transitions from time-domain truncation to frequency-domain filtering by introducing a low-pass filter in the RF output path. This dimensional change allows wideband signals to pass through without truncation artifacts, maintaining EVM performance across increasing bandwidths while preserving the digital polar transmitter's efficiency advantages.
3Reliability
If I/Q RF DAC is used to convert baseband data IQ in RF signal, then signal integrity is maintained, but double silicon area is required to deliver the same amount of power
Solution Approach 1:
The patent creates a digital copy of the baseband I and Q signals and processes them through separate digital channels until the final RF stage. By maintaining digital representations throughout the processing chain and only converting to analog at the final DAC stage, the system preserves signal integrity through precise digital manipulation while minimizing the area required compared to dual I/Q RF DAC architectures.
Data Source
AI summary
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.