In-Package RF Waveguides for High-Bandwidth Die-to-Die Links

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Solution Overview

Problem

Current techniques for connecting silicon dies in electronic packages, such as 3D die-to-die stacking, silicon interposers, and EMIB, face challenges with power delivery, cooling, cost, and limited bandwidth, particularly in achieving high-density and high-bandwidth interconnects.

Innovation Solution

In-package RF waveguides are formed in the package substrate to provide high-bandwidth chip-to-chip interconnects, using existing manufacturing processes, allowing for ultra-high bandwidth RF signal communication between silicon dies or tiles, with configurations like grounded co-planar and coaxial waveguides, and enabling seamless integration into existing manufacturing flows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If 3D die-to-die stacking with TSV connection is used, then vertical electrical connection between dies is achieved, but power delivery to top die is complicated and cooling of bottom die is detrimental

Engineering Contradiction:
Improvevertical electrical connectionVSAvoidpower delivery complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediate substrate layer with through-substrate vias that mediates the connection between stacked dies. This intermediate structure simplifies power delivery by providing dedicated power and ground paths through the substrate, separating them from signal paths and reducing complexity compared to direct TSV connections between dies.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If silicon interposer with TSV connection is used, then connections to silicon die are achieved, but interposer size, yield, and reticle size are limited making the technique costly

Engineering Contradiction:
Improveconnection to silicon dieVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the interconnection structure into modular components: die-level interconnects, substrate-level through-vias, and package-level routing. This segmentation allows each component to be optimized independently and manufactured using standard processes, avoiding the need for large, complex interposers and reducing manufacturing costs.

Inventive Principle:
Principle #1Segmentation

3Reliability

If EMIB with bridge is used to connect silicon dies, then interconnection between dies is achieved, but increased number of bridges limits substrate packaging and assembly

Engineering Contradiction:
Improveinterconnection between diesVSAvoidsubstrate packaging complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional bridge-based interconnects to three-dimensional through-substrate via structures. By routing connections vertically through the substrate rather than laterally through bridges, the design eliminates the need for multiple bridge structures and simplifies substrate packaging and assembly operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Productivity

If VHD interconnects with organic packages are used, then high density interconnection is achieved, but new tools and facilities are required making it cost intensive

Engineering Contradiction:
Improveinterconnect densityVSAvoidmanufacturing facility requirement
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent designs a multi-functional substrate structure that serves multiple purposes: mechanical support, electrical interconnection, signal routing, and thermal management. This universal structure can be manufactured using existing semiconductor and packaging processes, eliminating the need for specialized tools and facilities required by organic package VHD interconnects.

Inventive Principle:
Principle #6Universality (Multi-functionality)

5Quantity of substance

If interconnects with large area on wafer are used, then more interconnects can be provided, but wafer yields decrease and data rates become slow

Engineering Contradiction:
Improvenumber of interconnectsVSAvoidwafer yield
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent moves interconnect routing from the wafer plane to the vertical dimension using through-substrate vias. This allows multiple interconnects to be packed in a smaller footprint area on the wafer, increasing the number of interconnects per wafer while maintaining high yields and enabling faster data rates through shorter, more direct signal paths.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The RF waveguides offer ultra-high bandwidth RF signal communication, minimizing design and manufacturing resources, increasing wafer utilization and yields, and providing compact electronic packages with low I/O density while supporting high-frequency data transmission.

Implementation Method 1

In-package RF waveguides as high bandwidth chip-to-chip interconnects

Methodology Applied
Scientific EffectWaveguide: Waveguide (optics)

Data Source

PatentUS11894324B2In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same
Publication Date: 2024.02.06 INTEL CORP
  • US11894324B2 patent drawing
  • US11894324B2 patent drawing
  • US11894324B2 patent drawing

AI summary

In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.