RFC Diode Cathode Structure for Low Off-Loss and Breakdown Resistance

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Solution Overview

Problem

Existing power semiconductor devices face challenges in achieving high-speed operation and low off-loss while maintaining voltage holding capability and high-temperature performance, particularly due to issues with carrier lifetime control and increased leakage current during reverse bias.

Innovation Solution

The power semiconductor device incorporates a semiconductor substrate with a drift layer, a buffer layer, and a diffusion layer, featuring a two-layer cathode structure with specific impurity concentration profiles and crystal defect densities to optimize performance without relying on carrier lifetime control methods, enhancing contact properties and reducing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If carrier lifetime control method is used to shift trade-off characteristic to high-speed side, then switching loss is reduced, but voltage holding capability is deteriorated

Engineering Contradiction:
Improveswitching lossVSAvoidvoltage holding capability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The invention applies local quality by creating a cathode layer with non-uniform impurity concentration distribution, where a first region has higher impurity concentration than a second region. This localized variation in material properties enables different regions to perform different functions: the high-concentration region provides good contact properties for reducing switching loss, while the low-concentration region maintains voltage holding capability by preventing excessive carrier injection.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention changes the impurity concentration parameter within the cathode layer to resolve the contradiction. By establishing an impurity concentration gradient where the first region has higher concentration and the second region has lower concentration, the device achieves both low switching loss (through good contact in high-concentration region) and high voltage holding capability (through reduced carrier injection in low-concentration region).

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If conventional diffusion layer structure is used, then manufacturing is simplified, but off-loss increases and high-temperature operation is difficult to realize

Engineering Contradiction:
Improvediffusion layer structureVSAvoidoff-loss
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The invention applies local quality by dividing the cathode layer into regions with different impurity concentrations. The first region with higher impurity concentration provides excellent contact properties that reduce off-loss, while the overall structure maintains manufacturing simplicity. This localized differentiation allows the device to achieve low off-loss and high-temperature operation capability without significantly complicating the manufacturing process.

Inventive Principle:
Principle #3Local quality

3Speed

If carrier lifetime is reduced for high-speed operation, then switching performance improves, but leakage current during voltage holding increases

Engineering Contradiction:
Improveswitching speedVSAvoidleakage current
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The invention applies local quality by creating spatial variation in impurity concentration within the cathode layer. The first region with higher impurity concentration enables fast switching through good contact properties, while the second region with lower impurity concentration reduces leakage current during voltage holding by limiting excessive carrier injection. This localized differentiation resolves the contradiction between switching speed and leakage current.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20230268398A1Power semiconductor device and method for manufacturing power semiconductor device
Publication Date: 2023.08.24 MITSUBISHI ELECTRIC CORP
  • US20230268398A1 patent drawing
  • US20230268398A1 patent drawing
  • US20230268398A1 patent drawing

AI summary

In an RFC diode, a semiconductor substrate includes an n− drift layer, an n buffer layer, and a diffusion layer provided between and in contact with the n buffer layer and a second metal layer. The diffusion layer includes an n+ cathode layer provided in contact with the n buffer layer and the second metal layer in a diode region. The n+ cathode layer includes a first n+ cathode layer in contact with the second metal layer and a second n+ cathode layer provided between the first n+ cathode layer and the n buffer layer in contact with the n buffer layer. Crystal defect density of the first n+ cathode layer is higher than crystal defect density of another diffusion layer.