RFDAC Clock Partitioning for Lower Power and Higher Frequency
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Solution Overview
Problem
Radio Frequency Digital-to-Analog Converters (RFDACs) using IQ architecture suffer from lower efficiency and lower output power due to the need for broader bandwidth and complex decoding procedures, which increase power consumption and silicon die area, limiting their application in modern wireless communication systems.
Innovation Solution
The RFDAC architecture is modified to reduce the number of unit-cell power amplifiers activated by multiple clock components, allowing for reduced power consumption and simplified logic, while maintaining signal quality, by activating only a portion of the unit-cell power amplifiers for each phase component, such as (1/√2)×100% for IQ-RFDACs, which reduces fan-out and driven lines, leading to lower cross-talk and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If all unit-cell power amplifiers are activated in IQ architecture to maintain signal quality, then output power is improved, but power consumption increases
Solution Approach 1:
The patent activates only a portion of the unit-cell power amplifiers (specifically (1/√2)×100% for IQ-RFDACs) rather than all amplifiers, which reduces power consumption while maintaining adequate signal quality through selective activation of necessary amplifier cells
Solution Approach 2:
The patent modifies the activation parameter from 100% of unit-cell power amplifiers to a reduced percentage ((1/√2)×100%), changing the operational state of the amplifier array to achieve lower power consumption while preserving essential signal quality
2Adaptability or versatility
If multiple clock components are used to activate unit-cell power amplifiers, then operational flexibility is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes unnecessary clock components from the system, retaining only the essential clock signals needed for operation, thereby reducing the complexity of the decoding logic and control mechanisms while preserving operational flexibility
Solution Approach 2:
The patent uses simplified clock signal distribution where a reduced set of clock components controls the unit-cell power amplifiers, eliminating the need for complex multi-clock coordination while maintaining the ability to activate different amplifier subsets
3Power
If fan-out and driven lines are increased to activate more unit-cell power amplifiers, then output power is improved, but cross-talk and noise increase
Solution Approach 1:
The patent activates only a portion of the unit-cell power amplifiers rather than all amplifiers, which reduces the fan-out and number of driven lines, thereby minimizing cross-talk and noise while maintaining sufficient output power through selective amplifier activation
Data Source
AI summary
A RFDAC comprising an array of unit-cell power amplifiers, wherein the array comprises a first plurality of unit-cell power amplifiers, a second plurality of unit-cell power amplifiers, and a third plurality of unit-cell power amplifiers; wherein the first plurality of unit-cell power amplifiers are configured to operate in accordance with a first clock; wherein the second plurality of unit-cell power amplifiers are configured to operate in accordance with a second clock; wherein the third plurality of unit-cell power amplifiers are configured to operate in accordance with the first clock or the second clock. The RFDAC also comprising a decoder configured to output the first clock and an enablement signal of the first clock for the first plurality; output the second clock and an enablement signal of the second clock for the second plurality; distinguish between the first clock and the second clock for the third plurality.