RFDAC IQ Mismatch Compensation Using Digital Delay-Line Measurement
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Solution Overview
Problem
IQ mismatch in digital-to-analog converters (DACs) leads to error vector magnitude (EVM) degradation, particularly at higher frequencies, affecting the performance of radio-frequency DACs (RFDACs) due to misalignment of I and Q vectors.
Innovation Solution
A system is deployed in RFDACs to measure and compensate for IQ mismatch using CMOS digital integration, employing a latch circuit to measure phase-vectors as digital pulses and adjust delays to align I and Q signals, with a delay line and additive delay line coupled to capacitive elements to mitigate errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If quadrature signals are used for modulation in RFDAC, then signal transmission capability is improved, but IQ mismatch causes EVM degradation and performance reduction
Solution Approach 1:
The patent applies preliminary action by measuring the phase offset between I and Q signals in advance using a delay line and latch sensor, then compensating for the IQ mismatch before the actual signal transmission occurs. This pre-measurement and pre-compensation approach ensures that the modulation signals are properly aligned before being used, preventing EVM degradation while maintaining signal transmission capability.
2Measurement precision
If phase offset measurement is performed using delay line and latch sensor, then IQ mismatch detection precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog phase measurement mechanisms with a digital-based approach using a delay line and latch sensor. The delay line converts phase differences into time delays, and the latch sensor captures these timing differences as digital signals. This substitution of mechanical/analog measurement with electronic/digital measurement achieves high precision while keeping the implementation practical and integrated.
3Reliability
If additive delay line with capacitive elements is used for compensation, then IQ mismatch compensation effectiveness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service by using the same RFDAC device to generate test signals, measure its own phase offset, and compensate for its own IQ mismatch. The delay line and additive delay line are integrated within the device, allowing it to self-diagnose and self-correct without requiring external precision measurement equipment or complex external calibration systems. This reduces the burden on external manufacturing precision while achieving effective compensation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively mitigates IQ mismatch, improving RFDAC performance by reducing EVM degradation and ensuring accurate signal transmission.
Implementation Method 1
a delay line that includes a plurality of inverters selectively coupled to an output of the delay line via a first plurality of switches
Implementation Method 2
an additive delay line that includes a second plurality of switches coupled to a plurality of capacitive elements, wherein the additive delay line is coupled between a first inverter and a second inverter
Implementation Method 3
a latch sensor that includes an input coupled to the output of the delay line
Data Source
AI summary
The present disclosure relates to quadrature (IQ) signal mismatch in RFDACs. IQ mismatch is a non-ideality which occurs whenever I and Q vectors deployed to modulate the phase and the amplitude of RFDAC output signals are not aligned to be offset 90 degrees between each other. IQ mismatch may result in EVM degradation, and may be especially problematic for the RFDAC architecture because the RFDAC operates its digital-to-analog conversion at RF rate. A system may be deployed in the RFDAC to measure and compensate for IQ mismatch. The system may enable full-CMOS digital integration of both the measurement and compensation procedures. The system uses a simple flip-flop structure and exploits the fact that phase-vectors in CMOS logic are eventually digital pulses, and as such the mismatch between I and Q pulses with identical rise-fall time is simply measured as a skewed rise-to-rise and fall-to-fall delay between phases.