RF-DAC Timing Calibration for LO Switching Glitch Elimination
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Solution Overview
Problem
Existing RF-DACs experience glitches due to imperfections such as nonlinearities and data-dependent timing relationships between the Local Oscillator (LO) and data clock signals, leading to degraded spectral purity and linearity, especially when the LO and data clock frequencies are in an integer ratio.
Innovation Solution
A separate timing calibration system for the data switching of positive and negative LO signals is implemented, using different delays for the data signals based on whether the LO+ or LO− signal is switched, to prevent glitches without complex circuitry, ensuring proper phase alignment and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the data clock and LO clock frequencies are in an integer ratio with proper phase alignment, then glitches are eliminated and linearity is improved, but the device complexity increases due to timing calibration requirements
Solution Approach 1:
The patent applies preliminary action by performing timing calibration during the manufacturing process to pre-establish the correct phase relationship between data clock and LO clock. This ensures that when the device operates with integer ratio frequencies, the clocks are already properly aligned to prevent glitches, thereby improving linearity without adding complex runtime calibration systems.
Solution Approach 2:
The patent implements self-service by designing the RF-DAC to automatically maintain proper timing alignment through its inherent calibration circuitry. Once calibrated during manufacturing, the device self-corrects for timing variations without requiring external intervention or complex additional systems during operation, thus improving linearity while limiting complexity growth.
2Reliability
If separate timing calibration is implemented for LO+ and LO− signals, then glitches are eliminated and spectral performance is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by implementing separate timing calibration circuits for LO+ and LO− signals. This divides the calibration function into independent segments that can be individually optimized and tuned, allowing precise control over each signal path's timing characteristics to eliminate glitches and improve spectral performance while managing overall complexity through modular design.
3Manufacturing precision
If data transitions occur during high state of LO, then glitches are generated degrading linearity, but maintaining proper phase alignment requires complex timing control
Solution Approach 1:
The patent applies preliminary anti-action by implementing timing calibration that proactively prevents data transitions from occurring during the high state of the LO signal. The calibration system预先 establishes the correct timing relationship between data clock and LO clock, so that data transitions are guaranteed to occur during the low state of LO, thereby preemptively eliminating glitch generation and preserving linearity without requiring complex real-time control.
Data Source
AI summary
A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO− signals, and outputs a second controlled LO signal output to a sense circuit.