RFFE Port Aggregation Across Serial Buses for Higher Throughput
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Solution Overview
Problem
Mobile communication devices face challenges in achieving increased data throughput on serial buses due to limitations in clock frequency and the need for higher throughput as device complexity grows, particularly in radio frequency front-end (RFFE) circuits, which are constrained by maximum serial bus clock frequencies and legacy process nodes.
Innovation Solution
Implementing a multi-port data communication apparatus that utilizes multiple serial buses for data transmission, allowing data to be distributed across the lines of multiple aggregated serial buses, with a controller managing transactions to enhance throughput without increasing clock frequency or adding physical lines, and supporting port aggregation modes such as byte-level and bit-level interleaving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission is conducted over a single serial bus, then the system maintains simplicity and compatibility with legacy devices, but the data throughput is limited by maximum clock frequency
Solution Approach 1:
The patent combines multiple serial buses (first serial bus and second serial bus) into an aggregated communication channel. The controller distributes data across multiple data lines (second line of first serial bus and second line of second serial bus) to achieve higher throughput while maintaining compatibility with legacy single-bus devices through the first line of the first serial bus.
Solution Approach 2:
The serial bus system is designed to support multiple functions: it can operate in single-bus mode for legacy compatibility and in multi-bus aggregated mode for high-throughput applications. The controller dynamically selects the appropriate transaction mode based on the communication requirements.
2Productivity
If clock frequency is increased to boost data throughput, then transmission speed improves, but signal integrity issues arise and legacy device compatibility is lost
Solution Approach 1:
Instead of increasing clock frequency in the time domain, the patent expands the communication capacity by adding spatial dimensions - multiple data lines from aggregated serial buses. This allows parallel data transmission without increasing the clock rate, thereby maintaining signal integrity while achieving higher throughput.
3Productivity
If multiple serial buses are aggregated for high throughput, then data transmission capacity increases, but the system complexity and transaction management difficulty increase
Solution Approach 1:
The controller acts as an intermediary that manages the complexity of multi-bus aggregation. It handles data distribution across multiple buses, manages timing coordination, and abstracts the complexity from higher-level protocols. The controller implements the aggregation logic while presenting a simplified interface for data transmission.
4Productivity
If data is distributed across multiple serial buses, then throughput increases without increasing clock frequency, but the transaction protocol complexity increases
Solution Approach 1:
The data transmission protocol is segmented into different transaction types: first transactions that use only the first serial bus for simple operations, and second transactions that utilize both first and second serial buses for high-throughput operations. This segmentation allows the system to handle complex multi-bus transactions when needed while falling back to simpler single-bus transactions for routine operations.
Data Source
AI summary
A multi-port data communication apparatus includes a first port having a first physical interface circuit configured to couple the multi-port data communication apparatus to a first serial bus that has a first line and a second line, a second port having a second physical interface circuit configured to couple the multi-port data communication apparatus to a second serial bus that has a first line and a second line, and a controller. The controller is configured to use the first port during a first transaction restricted to transmissions over the first serial bus and use the first port and the second port in a second transaction in which data is transmitted over the second line of the first serial bus and the second line of the second serial bus in accordance with timing provided by a clock signal transmitted over the first line of the first serial bus.