RFIC Package Antenna Parallel-Plate Mode Suppression
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Solution Overview
Problem
Conventional RFIC chip packaging with integrated antennas or phased arrays faces challenges due to expensive components, extensive labor, and inefficiencies in antenna performance, particularly in millimeter-wave frequencies, where parallel-plate modes reduce antenna efficiency and increase coupling between antennas.
Innovation Solution
A multilayer chip package structure with conductive planes connected by vias, featuring a parallel-plate mode suppression mechanism using a grounded reflector and surrounding ground vias to form a cage around the antenna region, which reduces parallel-plate modes and enhances antenna performance by implementing cavity-backed aperture-coupled patch antennas or slot antennas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete components and waveguides are used for millimeter-wave RFIC packaging, then antenna performance and signal transmission are improved, but manufacturing cost and device complexity increase significantly
Solution Approach 1:
The patent combines the antenna structure with the RFIC package substrate, integrating what were previously separate discrete components into a unified structure. The antenna is formed using conductive patterns on the package substrate itself, eliminating the need for separate waveguide components and reducing overall packaging complexity while maintaining millimeter-wave performance
Solution Approach 2:
The patent introduces a specialized package substrate structure that acts as an intermediary between the RFIC and the external environment. This substrate includes ground planes, signal transmission lines, and antenna elements that mediate the signal path, replacing complex waveguide structures with planar transmission line technology that is easier to manufacture and integrate
2Ease of manufacture
If conventional package structures are used for integrated antennas, then manufacturing is simpler, but parallel-plate modes reduce antenna efficiency and increase coupling between antennas
Solution Approach 1:
The patent applies different structural characteristics to different regions of the package substrate. Ground planes are strategically positioned and dimensioned in specific local areas to control electromagnetic field distribution. The antenna elements have specific geometric configurations that locally suppress parallel-plate modes while maintaining radiation efficiency, allowing the structure to be manufactured using standard PCB techniques while achieving superior electromagnetic performance
3Length of moving object
If high gain antennas are used for long-distance wireless video, then transmission distance is improved, but beam width becomes very narrow making aiming difficult
Solution Approach 1:
The patent divides the antenna system into multiple independent antenna elements that can be individually controlled. By segmenting the antenna into an array of elements, the system can electronically steer the beam by adjusting the phase and amplitude of each element, maintaining narrow beam width for long-distance transmission while enabling electronic aiming adjustment without mechanical movement, thus improving ease of operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-cost, high-performance RFIC packages with integrated antennas, improving antenna efficiency and reducing manufacturing complexity, while maintaining easy manufacturability and effective feed line options for millimeter-wave applications.
Implementation Method 1
A parallel-plate mode suppression mechanism includes a grounded reflector and first grounded vias to at least partially form a cage round an antenna region
Implementation Method 2
A vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit
Data Source
AI summary
A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.