RFIC Package Bump Layout for High-Frequency Routing in Small Modules

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Solution Overview

Problem

Downsizing semiconductor packages while maintaining high frequency characteristics is challenging, as reducing the pitch of solder bumps complicates the placement and routing of high frequency circuits on substrates.

Innovation Solution

A semiconductor package design featuring two groups of solder bumps, where the second bump group with higher pitch connects high frequency and GND terminals, and the first bump group connects digital signal terminals, ensuring non-overlap with high frequency circuit blocks and symmetrical disposition to maintain high frequency characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the pitch of solder bumps is reduced to downsize the semiconductor package, then the package size is reduced, but it becomes difficult to dispose and route high frequency circuits on the substrate while maintaining high frequency characteristics

Engineering Contradiction:
Improvesemiconductor package sizeVSAvoidhigh frequency characteristics
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The solder bumps are segmented into two distinct groups: a first bump group with smaller pitch for digital signal terminals, and a second bump group with larger pitch for high frequency terminals. This segmentation allows each group to serve its specific function optimally - the first group enables package downsizing while the second group maintains high frequency characteristics by providing sufficient spacing for proper signal routing and reduced interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different pitch values are applied to different regions of the semiconductor package based on local requirements. The first bump group has a first pitch value optimized for digital signals and space efficiency, while the second bump group has a second pitch value (larger than the first) optimized for high frequency signal integrity. This local differentiation resolves the contradiction by allowing downsizing in regions where it doesn't compromise high frequency performance.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the pitch of solder bumps is reduced to downsize the substrate, then the substrate size is reduced, but the routing of high frequency circuits becomes more difficult

Engineering Contradiction:
Improvesubstrate areaVSAvoidcircuit routing complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The substrate mounting interface is segmented into two bump groups with different pitch characteristics. The second bump group with larger pitch provides adequate spacing for high frequency circuit routing, reducing routing complexity despite overall substrate downsizing. The first bump group with smaller pitch allows compact arrangement for digital circuits, enabling substrate area reduction without compromising routing feasibility for high frequency signals.

Inventive Principle:
Principle #1Segmentation

3Productivity

If solder bumps are densely arranged to reduce package size, then manufacturing cost is reduced, but high frequency signal integrity deteriorates

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention applies different spatial densities to different functional regions: the first bump group has higher density (smaller pitch) for cost-effective manufacturing and compact digital circuit connections, while the second bump group has lower density (larger pitch) to maintain signal integrity for high frequency terminals. This local quality differentiation resolves the contradiction between manufacturing efficiency and signal integrity by optimizing each region for its specific requirement.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240250052A1Semiconductor package and high frequency module
Publication Date: 2024.07.25 FUJIKURA LTD
  • US20240250052A1 patent drawing
  • US20240250052A1 patent drawing
  • US20240250052A1 patent drawing

AI summary

A semiconductor package includes an RFIC chip, a mold resin that surrounds the RFIC chip in a planar view, a plurality of solder bumps, and a plurality of redistributors that connect the RFIC chip to the plurality of solder bumps, wherein a first bump group disposed in a position that overlaps with the RFIC chip in the planar view, and a second bump group disposed in a position that overlaps with the mold resin in the planar view are included in the plurality of solder bumps, in the second bump group, at least a high frequency bump connected to a high frequency terminal of the RFIC chip, and a GND bump connected to a GND terminal of the RFIC chip are included, and a minimum pitch in the second bump group is larger than a minimum pitch in the first bump group.