RFIC Stacked Passive-On-Glass Inductor Quality Factor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CMOS technology for fabricating RF front modules in wireless communication devices results in poor quality factors for on-chip inductors due to the use of doped silicon substrates, leading to increased form factor and signal latency issues, as well as undesirable eddy currents and inductance effects.
Innovation Solution
The formation of RFICs in a Passive-On-Glass (POG) configuration using a dielectric substrate with vertical through-silicon vias (TSVs) for electrical connections and an electrical shield structure to shield electronic devices from passive components, allowing for improved coupling and reduced form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If on-chip inductors are formed over doped silicon substrate using existing CMOS process flow, then the manufacturing process is simple and widely used, but the quality factor of inductors deteriorates
Solution Approach 1:
The patent divides the RFIC into two separate substrates: a silicon substrate for active devices and a glass substrate for passive inductors. This segmentation allows each substrate to be optimized for its specific function, with glass providing superior Q-factor for inductors while silicon handles active device fabrication using standard CMOS processes.
Solution Approach 2:
The patent introduces an intermediary coupling mechanism through vertical through-silicon vias (TSVs) and inter-substrate coupling structures. These intermediaries enable electrical connection between the silicon substrate (active devices) and glass substrate (passive inductors) while minimizing parasitic effects and maintaining signal integrity.
2Object-affected harmful factors
If silicon areas under on-chip inductors are left blank to avoid eddy currents, then eddy current effects are reduced, but the form factor of RFIC increases
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture by moving passive inductors to a separate glass substrate above the silicon substrate. This dimensional change eliminates the need for blank silicon areas under inductors, as the inductors now reside in a different physical plane, thereby reducing the overall RFIC footprint while avoiding eddy current issues.
3Object-affected harmful factors
If on-chip inductors are displaced to a separate region and coupled through horizontal electrical feed-throughs, then eddy currents are avoided, but the footprint size and signal latency increase
Solution Approach 1:
Instead of using horizontal feed-throughs within the same substrate plane, the patent employs vertical through-silicon vias (TSV) to connect the silicon and glass substrates. This vertical connection approach in the third dimension reduces the horizontal routing distance, thereby minimizing footprint size and signal latency while still avoiding eddy current problems.
4Adaptability or versatility
If long metal traces are used to connect inductors to other components, then inductors can be placed separately, but undesirable inductance and signal latency increase
Solution Approach 1:
The patent utilizes vertical stacking to bring the inductors on the glass substrate into close proximity with the active devices on the silicon substrate. This 3D arrangement dramatically shortens the connection paths compared to planar layouts, reducing both signal latency and parasitic inductance while maintaining placement flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality factor of inductors by 50% compared to those on silicon substrates, reduces the form factor of RFICs, and minimizes signal latency and inductance issues, while maintaining performance and reducing processing complexity.
Implementation Method 1
an electrical shield structure formed to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate
Implementation Method 2
the silicon areas under the on-chip inductors are typically left blank in an effort to avoid the undesirable eddy currents induced in the silicon substrate due to the varying magnetic flux from the on-chip inductors
Implementation Method 3
Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate
Data Source
AI summary
Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.