RFIC Switch Multi-Finger Transistor Backside Gate Capacitive Tuning
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Solution Overview
Problem
The fabrication of RF switch transistors using semiconductor on insulator (SOI) technology is complicated by parasitic capacitance, which leads to increased off-state capacitance and reduced performance, especially when stacking transistors for desired power handling capabilities, as the breakdown voltage and off-state capacitance saturation occur due to parasitic capacitive coupling.
Innovation Solution
The implementation of a radio frequency (RF) integrated circuit (RFIC) switch multi-finger transistor design with dual gate transistors having varying gate lengths on both sides of the substrate, utilizing a layer transfer process to separate the active device from the substrate, and employing backside gates for capacitive tuning, allowing for dynamic adjustment of capacitance to achieve uniform scaling and reduced off-state leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are stacked to achieve desired power handling capability, then breakdown voltage is improved, but off-state capacitance saturation occurs due to parasitic capacitive coupling
Solution Approach 1:
The patent extracts the active device from the substrate using a layer transfer process, separating the transistor stack from the substrate to eliminate parasitic capacitive coupling. This involves forming a suspended structure where the active device layer is transferred to a handle substrate, removing the source of parasitic capacitance while maintaining the stacked configuration for power handling.
Solution Approach 2:
The patent introduces a vertical dimension by stacking transistors in series to achieve desired breakdown voltage and power handling capability. This multi-layer vertical arrangement allows multiple transistor channels to be combined, increasing power handling while the layer transfer process manages the parasitic capacitance issue in this new dimensional configuration.
2Manufacturing precision
If gate lengths are adjusted to tune capacitance, then off-state capacitance uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies different gate lengths to different transistors within the stack to locally tune capacitance characteristics. Each transistor can have optimized gate dimensions tailored to its position and function in the stack, allowing precise control over off-state capacitance distribution while maintaining overall device performance.
Solution Approach 2:
The patent changes geometric parameters (gate lengths and widths) of individual transistors in the stack to tune capacitance values. By varying these physical dimensions, the design achieves uniform off-state capacitance scaling across different stack configurations, compensating for position-dependent parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhances the performance of RF switch transistors by allowing for capacitive tuning, and provides more uniform scaling of off-state capacitance, thereby improving the power handling capability and reducing circuit delays and losses in RFIC switch stacks.
Implementation Method 1
capacitive tuning using a backside gate
Implementation Method 2
backside gates for capacitive tuning
Data Source
AI summary
A radio frequency (RF) integrated circuit (RFIC) switch multi-finger transistor includes a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate. The RFIC also includes a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate. The second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC switch multi-finger transistor.