RFID Tag Clock Extraction Using Adaptive Multi-Threshold Signals
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Solution Overview
Problem
Existing RFID receiver systems are not robust against antenna signal distortions, leading to unstable internal clock signals that disrupt data processing, particularly in conditions of weak magnetic fields or poor coupling.
Innovation Solution
A clock extraction stage that utilizes both the first and second received signals, employing three threshold levels and a threshold adaption circuit to ensure a stable internal clock signal, even in distorted conditions, by dynamically adjusting the threshold levels based on signal peak amplitudes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single threshold level is used to extract the clock signal, then the device complexity is reduced, but the reliability of the clock signal deteriorates under distorted antenna signal conditions
Solution Approach 1:
The clock extraction stage is segmented into multiple parallel threshold comparison circuits, each comparing the antenna signal against a different threshold level. This segmentation allows the system to evaluate multiple threshold conditions simultaneously, improving clock signal reliability under distorted signal conditions without significantly increasing overall device complexity.
Solution Approach 2:
The patent applies partial action by using a selective combination of threshold comparison results rather than requiring all thresholds to be met. The clock signal is generated based on partial satisfaction of threshold conditions, which maintains reliability while avoiding the complexity of processing all possible threshold combinations.
2Device complexity
If threshold levels are fixed, then the device complexity is reduced, but the adaptability to varying signal conditions deteriorates
Solution Approach 1:
The threshold adaptation circuit operates autonomously to monitor signal conditions and automatically adjust threshold levels without external intervention. This self-service mechanism enables the system to adapt to varying signal conditions dynamically, improving clock extraction reliability while minimizing the need for complex external control circuits.
Solution Approach 2:
The system implements feedback by continuously monitoring the antenna signal characteristics and using this information to adjust the threshold levels in real-time. The feedback loop ensures that the threshold levels remain optimal under varying signal conditions, enhancing adaptability without requiring complex manual calibration circuits.
3Reliability
If both first and second received signals are processed separately, then the reliability of clock signal improves, but the device complexity increases
Solution Approach 1:
The clock extraction stage merges the processing of both first and second received signals by using a unified set of threshold comparison circuits that simultaneously evaluate both signals. This merging approach maintains clock signal reliability through comprehensive signal evaluation while avoiding the complexity of completely separate processing paths for each signal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a robust and stable internal clock signal, ensuring reliable data processing even in the presence of signal distortions, thereby improving the reliability of RFID communication.
Implementation Method 1
a harvesting stage built to rectify a differential received signal provided between the first pin and the second pin of the receiver IC and built to provide a supply voltage referenced to a ground potential for the receiver IC
Implementation Method 2
the transmitter generated RF-Field is induced into the antenna of the tag and used to power the passive tag
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A receiver (19) exposed to a magnetic field with a specified carrier frequency (fres) in the RF frequency area and built to extract an internal clock signal (CLK) for processing of data with a receiver IC (20) of the receiver (19), which receiver (19) comprises: an antenna (8) built to receive an antenna signal (AS) and a tuning circuit (9) and built to provide a first received signal (RS1) at a first pin (10) of the receiver IC (20) and a second receiver signal (RS2) at a second pin (11) of the receiver IC (20), which receiver IC (20) comprises: a harvesting stage (12) built to rectify a differential received signal (UDIF) provided between the first pin (10) and the second pin (11) of the receiver IC (20) and built to provide a supply voltage (VDD) referenced to a ground potential (GRD) for the receiver IC (20); a clock extraction stage (18) built to provide a first threshold level (TH1) to switch the internal clock signal (CLK) with a rectangular signal shape between high and low potential, and that the clock extraction stage (18) is built to provide a second threshold level (TH2) and to provide a low threshold level (THL), which is closer to ground potential (GRD) than the first threshold level (TH1) and the second threshold level (TH2) and, which clock extraction stage (18) is built to switch the internal clock signal (CLK) from low potential to high potential, if the voltage (URS1) of the first received signal (RS1) referenced to ground potential (GRD) is above or passes above the first threshold level (TH1) and the voltage (URS2) of the second received signal (RS2) referenced to ground potential (GRD) is below or passes below the low threshold level (THL), which clock extraction stage (18) is built to switch the internal clock signal (CLK) from high potential to low potential, if the voltage (URS1) of the first received signal (RS1) referenced to ground potential (GRD) is below or passes below the low threshold level (THL) and the voltage (URS2) of the second received signal (RS2) referenced to ground potential (GRD) is above or passes above the second threshold level (TH2).