RFID Tag Clock Recovery Generator Synchronization During Load Modulation
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Solution Overview
Problem
RFID tags experience communication failures due to desynchronization of the bit grid of transmission and reception with the RFID reader, leading to a reduction in the effective operating distance, which can be attributed to the loss of field clock alignment during load modulation, resulting in communication holes.
Innovation Solution
A clock recovery generator in the RFID tag uses a phase-locked loop (PLL) clock synchronized with a clock recovery signal, which is paused during transmission, and resumes generation after a delay to maintain synchronization with the RF field clock, utilizing either a differential amplifier or an inverter for increased sensitivity and reliable detection, ensuring the PLL clock stays in sync with the field clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock recovery is paused during load modulation transmission, then the RFID tag can perform transmission operations, but the PLL clock drifts out of synchronization with the field clock causing communication failures
Solution Approach 1:
The patent applies preliminary action by calculating and storing the optimal delay value before transmission pauses occur. The delay value is pre-computed based on expected drift characteristics and stored in memory, so when clock recovery resumes after load modulation, the system can immediately apply the correct delay to re-synchronize the PLL clock with the field clock, preventing communication failures
Solution Approach 2:
The patent implements feedback by continuously monitoring the synchronization status between PLL clock and field clock, measuring the actual drift that occurs during transmission pauses. This feedback information is used to adjust and update the delay value for subsequent clock recovery operations, ensuring accurate resynchronization even under varying operating conditions
2Use of energy by moving object
If the RFID tag operates at half field clock frequency to reduce power consumption, then power consumption decreases and operating distance improves, but clock recovery complexity increases to maintain synchronization during transmission pauses
Solution Approach 1:
The system pre-calculates the delay value needed for clock resynchronization based on the known operating frequency (half field clock frequency) and stores it beforehand. This preliminary preparation simplifies the actual clock recovery operation during transmission pauses, as the system only needs to retrieve and apply the pre-computed delay value rather than performing complex real-time calculations
Solution Approach 2:
The clock recovery system serves itself by automatically adjusting the PLL clock phase using the pre-computed delay value without requiring external intervention or complex control logic. The system self-corrects the synchronization drift that occurs during transmission pauses, reducing the overall complexity of the clock recovery mechanism
Data Source
AI summary
There is provided, a method for clock recovery in a RFID tag, the method includes receiving a RF field from a RFID reader. A field clock is generated from the received RF field, from which a clock recovery signal is generated. The RF field is modulated to produce a RF modulation. Generation of the clock recovery signal is paused while the RF field is being modulated. A modulation envelope signal is generated and used for load modulation. Generation of the clock recovery signal at the end of the RF modulation is resumed after a delay of one clock cycle from a falling edge of the modulation envelope signal. In another embodiment of the method, instead of adding the delay, a differential amplifier is used to increase RF field detection sensitivity. The method and the RFID tag ensures synchronized resumption of a PLL clock and the clock recovery signal.