RFID Demodulator FIR Filtering for High-Q Tag Sensitivity
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Solution Overview
Problem
Passive RFID tags face limitations in sensitivity for downlink communication and transmit strength in uplink due to high quality-factor antennae, leading to reduced reading distance and increased manufacturing costs due to large component sizes.
Innovation Solution
A demodulator with a finite impulse response (FIR) filter arrangement replaces traditional continuous-time low-pass filters and envelope detectors, allowing for flexible equalization of RF signals and reducing component size and power consumption, thereby enhancing sensitivity and transmit strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional continuous-time low-pass filters and envelope detectors are used in the demodulator, then the circuit can perform basic signal demodulation, but the geometric size and power consumption increase, reducing sensitivity and reading distance
Solution Approach 1:
The patent changes the fundamental operating parameters of the filter by transitioning from continuous-time to discrete-time operation. The FIR filter uses switched capacitor circuits that operate at specific clock cycles, changing the time domain parameter from continuous to discrete. This parameter change enables smaller capacitor values and reduced power consumption while maintaining filtering functionality.
Solution Approach 2:
The patent substitutes traditional analog continuous-time filter circuits with a discrete-time FIR filter implementation using switched capacitors and digital logic. This replacement of the continuous analog system with a discrete system allows for more efficient power management and smaller component sizes, directly addressing the power consumption and sensitivity contradiction.
2Reliability
If traditional continuous-time low-pass filters and envelope detectors are used in the demodulator, then the circuit can perform basic signal demodulation, but the geometric size increases, reducing sensitivity and increasing manufacturing costs
Solution Approach 1:
The transition from continuous-time to discrete-time operation changes the spatial requirements of the filter components. The switched capacitor implementation uses smaller capacitor values compared to continuous-time filters, directly reducing the geometric area occupied by the filter circuitry while improving sensitivity through better signal processing.
Solution Approach 2:
The FIR filter is implemented by segmenting the filtering function into discrete time steps using multiple switched capacitor circuits operating at different phases. This segmentation allows the filter to be distributed across smaller individual components rather than requiring a large continuous-time filter structure, reducing overall geometric size.
3Stability of the object's composition
If high quality-factor antennae are used in passive RFID tags, then the antenna resonance is improved, but the sensitivity for downlink communication and transmit strength in uplink are reduced
Solution Approach 1:
The discrete-time FIR filter provides more accurate signal processing that can better compensate for the effects of high quality-factor antenna characteristics. By using multiple tapped delay elements and weighted summation, the filter can adaptively process the received signal to overcome the narrow bandwidth and resonance effects of high Q-factor antennas, improving demodulation sensitivity.
4Ease of manufacture
If traditional demodulator circuits are used, then the implementation is straightforward, but the power consumption and component size increase, leading to higher manufacturing costs
Solution Approach 1:
The patent replaces power-hungry continuous-time analog filter circuits with a discrete-time FIR filter implementation using switched capacitors and digital logic gates. This substitution reduces dynamic power consumption significantly while the regular structure of the FIR filter makes it well-suited for standard CMOS fabrication, reducing manufacturing costs despite the increased transistor count.
Data Source
AI summary
An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.