RFID Tag Oscillator Calibration via Digital Frequency Division
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Solution Overview
Problem
Traditional RFID tags require frequent recalibration of their oscillation circuits when entering a new 'read zone' due to volatile memory, which wastes time and consumes power, and they rely on analog circuits that occupy significant space and consume more power compared to digital circuits.
Innovation Solution
The implementation of a frequency division circuit in RFID tags that can calibrate the oscillator frequency using a combination of programmable and fixed counters, allowing for efficient frequency adjustment and reducing the need for recalibration by using digital circuitry and non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a variable oscillator is used to generate modulation frequency, then the RFID tag can transmit information at the correct frequency, but the analog circuit occupies significant space and consumes large power
Solution Approach 1:
The patent replaces the analog variable oscillator with a digital counter circuit that divides the carrier frequency to generate the modulation frequency. This substitution of digital logic for analog circuitry significantly reduces power consumption while maintaining frequency accuracy through programmable division ratios.
Solution Approach 2:
The patent changes the approach from varying oscillator parameters (analog control) to changing counter division ratios (digital programming). The modulation frequency is generated by programming the counter to divide the carrier frequency by a specific ratio, allowing flexible frequency control without power-hungry analog components.
2Speed
If volatile memory is used to store modulation frequency, then the frequency can be quickly accessed, but the oscillator must be recalibrated every time the tag enters a new read zone
Solution Approach 1:
The patent performs frequency calibration in advance by measuring the actual carrier frequency when first received and pre-calculating the appropriate counter division ratio. This preliminary calibration result is stored in non-volatile memory, eliminating the need for recalibration when entering new read zones and reducing time loss.
Solution Approach 2:
The patent creates a copy of the calibrated frequency information and stores it in non-volatile memory. This copied calibration data can be retrieved without recalibration, allowing the system to maintain fast frequency access while avoiding repeated calibration measurements and reducing time loss.
3Adaptability or versatility
If an analog variable oscillator is used, then frequency can be adjusted continuously, but the circuit requires large real estate and consumes more power compared to digital circuits
Solution Approach 1:
The patent replaces the analog variable oscillator with a digital counter circuit that divides the carrier frequency to generate the modulation frequency. This substitution of digital logic for analog circuitry significantly reduces power consumption while maintaining frequency accuracy through programmable division ratios.
Solution Approach 2:
The counter circuit serves multiple functions: it divides the carrier frequency to generate modulation frequency, and its division ratio can be programmed to adapt to different frequency requirements. This universal digital circuit replaces specialized analog oscillators, reducing overall circuit area while maintaining adaptability.
Data Source
AI summary
A system and method is provided for using a frequency division circuit to produce a desired frequency in a radio frequency identification transponder (RFID tag). In a preferred embodiment of the present invention, an RFID tag includes a frequency division circuit connected to a logic circuit and a oscillator. The logic circuit is adapted to identify at least one frequency associated with a received RF signal (e.g., the frequency of the signal, a frequency identified by the signal, etc.). This frequency is then used by the frequency division circuit to calibrate the frequency provided by the oscillator. In one embodiment of the present invention, the frequency division circuit includes at least one variable counter adapted to divide the frequency provided by the oscillator (i.e., the oscillation frequency) by a programmable factor to produce a desired frequency. The desired frequency is then provided to the logic circuit and used to modulate a received RF signal. In another embodiment of the present invention, the frequency division circuit further includes at least one fixed counter, wherein the fixed counter is not programmable. In this embodiment, the fixed counter is used to produce a particular (lower) frequency, and the variable counter is used to produce the desired frequency. Such an embodiment, for example, can be used to decrease the amount of time required to produce a desired frequency (e.g., by starting with a lower fixed frequency) and increase the amount of time available to perform alternate functions (e.g., communicate with external devices, etc.).