RFID Device Nonvolatile Ferroelectric Memory Voltage Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
RFID devices with FeRAMs face high power consumption due to supplying high voltage to all areas of the memory, including peripheral regions, which is unnecessary and inefficient.
Innovation Solution
A RFID device design that selectively supplies a high voltage only to the memory cell array area and a low voltage to the peripheral areas, optimizing power usage by utilizing a voltage multiplier and voltage doubler to generate and distribute voltages accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is supplied to all areas of the memory including peripheral regions, then the memory cell array area can operate properly, but power consumption increases unnecessarily
Solution Approach 1:
The memory device is segmented into two distinct voltage domains: a first voltage domain for the memory cell array area requiring high voltage (VDD2), and a second voltage domain for peripheral circuits operating at low voltage (VDD). This segmentation allows each area to receive only the voltage level it needs, eliminating unnecessary power consumption in peripheral regions while maintaining proper operation in the memory cell array.
Solution Approach 2:
Different voltage levels are applied to different spatial regions of the memory device. The memory cell array area receives high voltage (VDD2) to ensure proper operation of the ferroelectric capacitors, while peripheral circuits receive low voltage (VDD). This local differentiation of voltage quality optimizes power consumption by matching voltage supply to the actual operational requirements of each region.
2Device complexity
If high voltage is supplied to peripheral areas, then voltage requirements are simplified, but power consumption increases due to unnecessary high voltage supply
Solution Approach 1:
The voltage supply system is segmented into multiple independent domains with dedicated voltage generation and distribution paths. A first voltage line supplies high voltage (VDD2) only to the memory cell array area, while a second voltage line supplies low voltage (VDD) to peripheral circuits. This segmentation manages complexity through structured organization while achieving power savings.
Solution Approach 2:
The voltage supply system dynamically adapts voltage levels to the specific operational needs of different memory regions. Rather than applying a uniform high voltage throughout, the system dynamically provides high voltage only where required (memory cell array) and low voltage elsewhere (peripheral circuits), optimizing the balance between operational requirements and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption by ensuring only the necessary areas receive high voltage, thereby enhancing the energy efficiency of the RFID device.
Implementation Method 1
The voltage multiplier 21 generates a power voltage VDD of the RFID device in response to the radio frequency signal applied from the antenna 10
Implementation Method 2
The voltage doubler 25 boosts the power voltage VCC applied from the voltage multiplier 21 to supply a boosting voltage VDD2 having a swing width twice as large as the power voltage VDD to the memory 40
Implementation Method 3
it utilizes the high residual polarization characteristic of the ferroelectric substance in which data is not deleted even after an electric field is eliminated
Data Source
AI summary
A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal.