RFID Interrupt Controller Circuit for FRAM Memory Access
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Solution Overview
Problem
Current passive RFID tags using EEPROM memory are inefficient for high-throughput applications due to slow data transfer rates, and existing protocols are not optimized for faster memory technologies like FRAM, which are needed to handle increased data demands in environments such as factories and toll collection.
Innovation Solution
The implementation of an interrupt controller circuit with a memory access control system that includes a memory, memory access control circuit, RFID interface, secondary interface, and interrupt manager, optimized for FRAM-based RFID tags, which uses a modified serial interface and memory pointer mechanism to enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If EEPROM memory is used in passive RFID tags, then the system is simple and reliable, but the data transfer rate is slow and throughput is limited
Solution Approach 1:
The patent changes the memory technology parameter from EEPROM to FRAM (Ferroelectric Random Access Memory), which inherently provides faster write and read operations. This parameter change enables the system to achieve higher data transfer rates and throughput while maintaining compatibility with existing RFID protocols
Solution Approach 2:
The patent introduces a dynamic memory access control mechanism that includes an interrupt manager and memory access control circuit. These components dynamically manage memory access requests from both the RFID interface and secondary interfaces, optimizing data transfer operations based on real-time system state and priority requirements
2Productivity
If faster memory technologies like FRAM are used, then data throughput increases, but the existing EEPROM-related protocol is not optimized for the new memory technology
Solution Approach 1:
The patent creates a universal memory access control system that can handle multiple types of memory operations (read, write, block write) and multiple interface types (RFID interface and secondary interfaces) through a single integrated architecture. The interrupt manager and memory access control circuit work together to provide protocol-agnostic memory access, making the system adaptable to different memory technologies and communication protocols
Solution Approach 2:
The patent introduces an interrupt manager as an intermediary component between the memory and the various interfaces. This intermediary handles memory access control, arbitration, and coordination, allowing the system to optimize data throughput for FRAM while maintaining compatibility with existing RFID protocols and adding support for secondary interfaces
3Adaptability or versatility
If multiple interfaces are added to the memory access control circuit, then interface versatility increases, but device complexity increases
Solution Approach 1:
The patent segments the memory access control functionality into distinct modular components: an interrupt manager that handles interrupt processing and memory access arbitration, and a memory access control circuit that manages actual memory operations. This segmentation allows the system to support multiple interfaces (RFID and secondary interfaces) while keeping each component's complexity manageable through clear functional separation
Data Source
AI summary
A RFID system includes an RFID controller incorporating a serial bus master coupled via a serial bus to a serial bus slave device, whereby the RFID controller controls power supply and/or power mode of the salve device in order that the slave device is powered and able to communicate with the RFID controller in response to RFID commands received from an RFID reader, and unpowered or in a low power mode otherwise.