RFID Tag On-Chip Antenna Substrate Energy Loss
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Solution Overview
Problem
The high cost and inefficiency of traditional RFID tags due to off-chip antennas, which are incompatible with CMOS technology and result in significant energy loss on silicon substrates, limiting their application and reliability.
Innovation Solution
The integration of a deep opening array in the silicon substrate beneath the on-chip antenna layers, formed using standard CMOS processes, reduces substrate energy loss and enhances antenna performance by lowering resistivity and thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If off-chip antenna is used, then antenna performance is improved, but manufacturing cost increases and CMOS compatibility deteriorates
Solution Approach 1:
The patent merges the antenna structure with the CMOS circuit fabrication process by integrating the antenna into the same manufacturing flow. The antenna is formed as part of the semiconductor device structure, allowing it to be fabricated using standard CMOS processes rather than requiring separate off-chip antenna assembly, thus reducing manufacturing cost while maintaining antenna performance.
Solution Approach 2:
The patent creates a universal manufacturing process that can produce both the CMOS circuitry and the antenna using the same fabrication steps. The antenna structure is designed to be compatible with standard CMOS technology, enabling a single manufacturing process to create a fully functional RFID tag with integrated antenna and circuitry, eliminating the need for separate antenna fabrication and assembly processes.
2Reliability
If off-chip antenna is used, then antenna performance is improved, but device size increases
Solution Approach 1:
The patent combines the antenna and circuitry into a single integrated structure that occupies a compact area on the semiconductor chip. By eliminating the need for external antenna components and coupling wires, the overall device footprint is significantly reduced while maintaining the electrical performance of the antenna through direct integration with the CMOS circuitry.
3Reliability
If off-chip antenna with coupling wires is used, then antenna performance is improved, but system stability deteriorates due to parasitic inductance
Solution Approach 1:
The patent extracts and eliminates the coupling wires from the system by directly integrating the antenna with the CMOS circuitry. This removal of the intermediate coupling element eliminates the parasitic inductance that caused instability, while the antenna performance is maintained through direct electrical connection and optimized antenna-circuit integration.
4Ease of manufacture
If on-chip antenna is integrated, then manufacturing cost decreases and CMOS compatibility improves, but energy loss on substrate increases
Solution Approach 1:
The patent applies local quality modification by creating a low-resistivity region specifically at the antenna location on the substrate. Through localized doping or material modification beneath the antenna, the substrate properties are changed only in the critical area to reduce energy loss, while the rest of the substrate maintains its normal characteristics. This allows on-chip antenna integration with reduced substrate losses.
Solution Approach 2:
The patent changes the physical parameters of the substrate at the antenna region by modifying the resistivity through localized doping or material deposition. This parameter change reduces the energy loss in the substrate beneath the antenna, enabling efficient on-chip antenna operation while maintaining compatibility with standard CMOS manufacturing processes.
5Ease of manufacture
If standard CMOS processes are used for antenna fabrication, then manufacturing cost decreases, but antenna performance may deteriorate due to substrate losses
Solution Approach 1:
The patent applies local quality modification by creating a low-resistivity region specifically at the antenna location on the substrate. Through localized doping or material modification beneath the antenna, the substrate properties are changed only in the critical area to reduce energy loss, while the rest of the substrate maintains its normal characteristics. This allows on-chip antenna integration with reduced substrate losses.
Solution Approach 2:
The patent uses composite material structures by combining the standard CMOS substrate with localized low-resistivity regions created through doping or material deposition. This composite approach maintains the benefits of standard CMOS manufacturing while adding specialized low-loss regions beneath the antenna to preserve antenna performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-performance on-chip antennas to be fabricated using standard CMOS manufacturing processes, reducing energy loss and increasing the efficiency of RFID tags while maintaining compatibility with existing technologies.
Implementation Method 1
reduces substrate energy loss and enhances antenna performance by lowering resistivity and thermal conductivity
Data Source
AI summary
A radio frequency identification (RFID) device is disclosed. The RFID device includes a silicon substrate having a top side and a bottom side. The RFID device also includes a plurality of circuitry layers formed on the top side of the substrate, and the plurality of circuitry layers include at least a core circuitry and an on-chip antenna. Further, the RFID device includes a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers. The plurality of deep openings are arranged in an array and through a substantial portion of the substrate, and a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers.