RFSOI Wafer Superlattice Growth for Higher Mobility, Lower Defects
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Solution Overview
Problem
Existing semiconductor technologies face challenges in enhancing the performance of semiconductor devices beyond current capabilities, particularly in achieving improved charge carrier mobility and reducing defects in semiconductor-on-insulator (SOI) wafer fabrication.
Innovation Solution
A method involving epitaxial deposition, including an anneal process on a SOI substrate, followed by an in-situ etch to reduce the thickness of a semiconductor layer, and the formation of a superlattice layer with stacked groups of base semiconductor monolayers and non-semiconductor monolayers constrained within the crystal lattice, to enhance charge carrier mobility and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial deposition is used to form semiconductor layers, then manufacturing simplicity is maintained, but charge carrier mobility is insufficient
Solution Approach 1:
The semiconductor layer is segmented into a superlattice structure composed of multiple alternating monolayers of different materials (e.g., Si/SiGe, Si/SiC). This segmentation creates a periodic potential landscape that enhances carrier mobility through quantum confinement and reduced scattering, while the modular nature of the superlattice allows for systematic fabrication using standard epitaxial techniques.
Solution Approach 2:
The invention employs composite material structures where alternating layers of different semiconductor materials (e.g., silicon and silicon-germanium) are combined to form a superlattice. This composite structure exploits the beneficial properties of each material to achieve enhanced carrier mobility, with the periodic interface providing quantum mechanical effects that improve transport while remaining compatible with existing fabrication processes.
2Manufacturing precision
If thicker semiconductor layers are used, then device manufacturing is simplified, but defect density increases
Solution Approach 1:
Instead of using a single thick semiconductor layer, the invention segments the layer into multiple thin alternating monolayers forming a superlattice. Each individual monolayer can be grown with high precision and low defect density using epitaxial techniques, and the cumulative thickness achieves the desired overall layer thickness while maintaining high quality throughout.
Solution Approach 2:
The invention changes the structural parameters by transitioning from a homogeneous thick layer to a periodic superlattice structure with alternating materials. This parameter change allows for better control of crystal growth, reduced defect propagation, and improved interface quality, as each thin layer can be optimized independently during the epitaxial growth process.
3Reliability
If strained material layers are introduced to enhance mobility, then charge carrier mobility improves, but fabrication complexity increases
Solution Approach 1:
The invention uses composite material systems where layers of different materials (e.g., Si and SiGe) are alternated to create built-in strain through lattice mismatch. This strain is engineered to enhance carrier mobility in the channel region. The strain is automatically generated during epitaxial growth by the differential lattice constants of the alternating materials, eliminating the need for separate strain introduction steps.
Solution Approach 2:
The invention changes material composition parameters by incorporating materials with different lattice constants in alternating layers. This compositional parameter change creates controlled strain fields that enhance carrier mobility. The strain magnitude and distribution are controlled by adjusting the thickness and composition ratios of the alternating layers, allowing optimization without adding process complexity.
4Reliability
If superlattice structures are formed with multiple alternating monolayers, then charge carrier mobility is enhanced through reduced effective mass, but manufacturing precision requirements increase
Solution Approach 1:
The superlattice is segmented into repeating units of alternating monolayers, where each unit can be grown with controlled thickness. The periodic structure allows for self-consistent growth conditions, and the thin monolayer thickness (on the order of nanometers or fewer) enables precise control of the potential landscape, thereby reducing carrier effective mass and enhancing mobility through quantum mechanical effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method effectively enhances charge carrier mobility by reducing the effective mass of carriers and improving the quality of interfaces, while also reducing defects and enabling the formation of high-quality semiconductor devices with improved performance characteristics.
Implementation Method 1
performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer
Implementation Method 2
performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness
Implementation Method 3
forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Data Source
AI summary
A method for making a semiconductor device may include, in an epitaxial deposition tool, performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness. The method may also include, in the epitaxial deposition tool, performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness, and forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.