RGMII Timestamping Using DLL Phase Sampling
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Solution Overview
Problem
Achieving synchronization among nodes in a distributed area network is challenging, particularly in time-sensitive systems, due to errors introduced by network topology and the complexity of timestamping accuracy, which affects the precision of clock synchronization.
Innovation Solution
The use of timestamp circuitry that generates sample clocks from the receive clock signal to produce a timestamp offset, allowing for improved timestamp precision by calculating the instantaneous phase offset between local clocks of neighboring nodes, which can be included in timing frames to adjust synchronization, while maintaining low power consumption by using a 125 MHz internal local clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-precision timestamping is implemented using external high-frequency clocks, then timestamp accuracy is improved, but power consumption increases
Solution Approach 1:
The patent enables the existing 125 MHz DLL to serve dual purposes: its original function of clock recovery and a new function of generating precise timestamp samples. By configuring the DLL to output multiple delayed clock phases and using these phases to sample incoming data edges, the system achieves high-precision timestamping without requiring external high-frequency clocks, thereby maintaining low power consumption while improving timestamp accuracy to +/- 1 nsec resolution
Solution Approach 2:
The existing DLL circuitry is made multi-functional by enabling it to generate both the clock recovery signal and the timestamp sampling signals. The DLL's ability to produce multiple delayed clock phases allows it to simultaneously perform clock synchronization and precise timestamp generation, eliminating the need for separate dedicated timestamping hardware and reducing overall system power consumption
2Measurement precision
If multiple DLLs are added to achieve enhanced timestamping, then timestamp precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing DLL multi-functional by enabling it to generate both clock recovery signals and timestamp sampling signals. The DLL is configured to output multiple delayed clock phases that are used to sample incoming data edges, allowing a single DLL circuit to perform both clock synchronization and precise timestamp generation without adding additional DLL hardware
Solution Approach 2:
The patent combines the timestamping function with the existing clock recovery DLL by integrating the timestamp sampling logic into the same DLL circuitry. The delayed clock phases generated by the DLL are multiplexed to serve both clock recovery and timestamp sampling purposes, merging two functions into a single integrated solution that reduces overall system complexity
3Measurement precision
If higher frequency clocks are used for timestamping, then timestamp resolution is improved, but power consumption increases
Solution Approach 1:
The patent enables the existing 125 MHz DLL to generate precise timestamp samples by producing multiple delayed clock phases and using these phases to sample incoming data edges. This approach achieves high timestamp resolution without requiring external high-frequency clocks, allowing the system to maintain low power consumption while achieving +/- 1 nsec timestamp accuracy
Solution Approach 2:
The patent changes the operational parameters of the existing DLL by configuring it to output multiple delayed clock phases with specific phase relationships. By adjusting the DLL's delay settings and phase outputs, the system achieves high-resolution timestamping at the lower 125 MHz frequency, eliminating the need to increase clock frequency and associated power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances timestamp accuracy to a resolution of +/- 1 nsec, reducing synchronization errors and improving the precision of timing in network nodes, especially in complex factory automation applications.
Implementation Method 1
produce sample signals from the receive clock signal using a delay locked loop (DLL) circuit of the RGMII
Data Source
AI summary
A network node device of an area network includes physical layer (PHY) circuitry configured to transmit and receive frames of data via a communication link of the communication network; medium access layer (MAC) circuitry; a receive interface between the PHY circuitry and the MAC circuitry, and timestamp circuitry. The receive interface includes a receive clock signal and a DLL. The timestamp circuitry is configured to produce multiple sample signals derived from the receive clock signal using the DLL and a local clock signal of the network node, and produce a timestamp offset using the multiple sample signals. The timestamp offset is representative of an instantaneous phase offset between a local clock of the network node and a local clock of a neighbor node of the network node.