Rhombus Wafer-Level Chip Package for Solder Ball Spacing
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Solution Overview
Problem
Conventional wafer level chip scale packages with rectangular or square shapes face limitations in miniaturization due to fixed spacing requirements for solder balls, preventing reduction in semiconductor chip size.
Innovation Solution
A wafer level chip scale package with a rhombus shape is introduced, featuring a semiconductor chip with 120° and 60° interior angles, allowing for a symmetric arrangement of solder balls that reduces chip size by approximately 5 to 12% while maintaining compatibility with conventional semiconductor manufacturing equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If solder balls are arranged on a rectangular or square semiconductor chip with fixed spacing requirements, then the chip can be manufactured using conventional processes, but the chip size cannot be reduced further due to spacing constraints between solder balls and chip edges
Solution Approach 1:
The patent applies asymmetry by changing the chip shape from a conventional symmetric rectangular or square form to a rhombus shape with specific interior angles (60° and 120°). This asymmetric geometric transformation allows solder balls to be arranged more efficiently within the chip area, reducing the overall chip size while maintaining adequate spacing between solder balls and chip edges. The rhombus geometry creates optimized diagonal arrangements that accommodate solder ball spacing requirements with smaller dimensional footprint.
2Length of moving object
If the chip size is reduced to meet miniaturization demands, then portable electronic devices can be made smaller, but the spacing between solder balls and chip edges becomes insufficient, risking short circuits
Solution Approach 1:
The rhombus shape with 60° and 120° interior angles creates an asymmetric geometry that optimizes the distribution of solder balls away from the chip edges. This geometric configuration naturally provides sufficient spacing between solder balls and chip edges even when the overall chip size is reduced, thereby maintaining reliability and preventing short circuits while achieving miniaturization.
Solution Approach 2:
The patent utilizes dimensional optimization by arranging solder balls along the diagonal axes of the rhombus-shaped chip rather than along the conventional rectangular edges. This diagonal arrangement in a different spatial dimension allows for reduced chip size while maintaining adequate clearance between solder balls and chip boundaries, effectively solving the spacing constraint problem.
3Length of moving object
If a new chip shape is introduced to reduce size, then miniaturization can be achieved, but compatibility with conventional semiconductor manufacturing equipment may be compromised
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the chip (shape and interior angles) while keeping the fundamental manufacturing process parameters compatible with conventional equipment. The rhombus shape with specific 60° and 120° angles can be fabricated using standard semiconductor processing techniques, allowing miniaturization without requiring new manufacturing equipment.
Data Source
AI summary
The present disclosure relates to a wafer level chip scale package with a rhombus shape which includes a semiconductor chip with a rhombus shape and a solder ball array including a plurality of solder balls formed on one surface of the semiconductor chip. Among four interior angles of the semiconductor chip, two of the four interior angles facing each other in a short diagonal direction are approximately 120°, and two of the four interior angles facing each other in a long diagonal direction are approximately 60°.