Ribbon CFET Channel Materials for Stacked NMOS and PMOS
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Solution Overview
Problem
Conventional processing flows for stacking complementary NMOS and PMOS FETs are unsuited to optimize performance and area utilization in integrated circuits, and existing methods do not allow for the use of materials optimized for each transistor type, leading to inefficiencies and increased complexity.
Innovation Solution
The use of novel processing techniques to segregate and optimize channel materials for NMOS and PMOS transistors in a stacked configuration, employing different materials for each type, such as silicon for NMOS and silicon germanium for PMOS, with distinct spacer materials and sacrificial layers to enable efficient fabrication and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional processing flows are used to stack complementary NMOS and PMOS FETs, then device stacking is achieved, but performance optimization and area utilization are compromised
Solution Approach 1:
The patent segments the CFET fabrication process into distinct stages: forming sacrificial layers, depositing channel materials, creating spacers, and selective removal. This segmentation allows independent optimization of each step, enabling better die-area utilization while maintaining device performance through controlled material placement and removal sequences.
Solution Approach 2:
The patent employs preliminary actions by pre-forming sacrificial layers (silicon or silicon germanium) before channel material deposition, and by using spacer materials to predefine critical dimensions. These preliminary structures guide subsequent processing steps, ensuring optimal area utilization and performance are achieved simultaneously through predetermined geometric constraints.
2Reliability
If different materials are used for NMOS and PMOS channels, then performance is optimized, but processing complexity increases
Solution Approach 1:
The patent applies local quality by using different channel materials (silicon for NMOS, silicon germanium for PMOS) in specific localized regions of the stacked structure. Each material is placed where it provides optimal electrical characteristics for its intended transistor type, achieving performance optimization without requiring completely different processing flows for each device type.
Solution Approach 2:
The patent uses spacer materials as intermediaries between the channel materials and gate structures. These spacers serve as mediators that define critical dimensions and provide etch selectivity, allowing different channel materials to be processed through a unified flow while maintaining precise geometric control and reducing overall processing complexity.
3Ease of manufacture
If existing processing methods are used, then fabrication is straightforward, but materials optimized for each FET type cannot be employed
Solution Approach 1:
The patent changes key processing parameters by introducing sacrificial layers with specific etch selectivities and spacer materials with defined deposition thicknesses. These parameter changes enable the use of optimized channel materials while maintaining a relatively simple unified processing flow, as the sacrificial and spacer structures provide controlled geometric constraints that work across different material systems.
Data Source
AI summary
Integrated circuit (IC) devices having stacked, complementary transistors with channels of different compositions. A device includes transistors with first and second groups of nanoribbons vertically aligned in a stack of nanoribbon channels coupling first and second sources and drains, and one of the first and second nanoribbons has a semiconductor element absent from the other. The first and second groups of nanoribbons extend between first and second spacers, which may have different compositions. First and second hardmasks with different compositions may be used process the first and second groups of nanoribbons separately. A masking layer having the composition of one of the first and second nanoribbons may mask the other of the first and second nanoribbons.