Ribbon CFET Metal-Gate Integration for Multi-Threshold Logic
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Solution Overview
Problem
The integration of complementary field effect transistors (CFETs) in logic devices and memory devices faces challenges in balancing performance requirements with power constraints, particularly in applications involving accelerators like Tile Matrix Multiply (TMUL) units and Vision Processing Units (VPU), where existing transistor architectures struggle to optimize threshold voltage for efficient power management.
Innovation Solution
The implementation of a CFET structure with multiple threshold voltages (Vt) integrated into stacked CFET devices using volumeless nD and pD for Vt separation, allowing independent control of threshold voltages through different combinations of N and P dipoles at the channel interfaces, enabling a balance between performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single threshold voltage is used in CFET devices, then the device structure is simple, but the ability to balance performance and power consumption is limited
Solution Approach 1:
The CFET device is segmented into multiple independent threshold voltage control mechanisms: N-type dipole layer, P-type dipole layer, and metal gate stack with adjustable work function. Each segment can be independently tuned to achieve different threshold voltage combinations, enabling flexible adaptation to various performance and power requirements without requiring completely different device structures.
Solution Approach 2:
The patent employs parameter changes by adjusting the work function of the metal gate stack, the dipole moment of the N-type and P-type dipole layers, and their respective thicknesses. These parameter variations allow continuous tuning of threshold voltages for both nMOS and pMOS transistors within the CFET, providing versatile control while maintaining a unified device architecture.
2Use of energy by moving object
If higher threshold voltage is used, then power consumption is reduced, but device speed and performance decrease
Solution Approach 1:
The CFET device implements dynamic threshold voltage control where the N-type and P-type dipole layers can be independently adjusted to create different threshold voltage combinations. This dynamic adaptability allows the device to switch between low-power high-threshold mode and high-speed low-threshold mode based on operational requirements, resolving the static trade-off between power consumption and switching speed.
Solution Approach 2:
Different regions of the CFET device (nMOS and pMOS transistors) are assigned different threshold voltage characteristics through localized dipole layer configurations. This allows one transistor to operate at high threshold for low power while the other operates at low threshold for high speed, enabling simultaneous optimization of power and performance within the same device structure.
3Productivity
If multiple threshold voltages are integrated into CFET devices, then performance optimization for specific applications is enabled, but manufacturing complexity increases
Solution Approach 1:
The CFET device structure serves multiple functions through a unified architecture: the N-type and P-type dipole layers together with the metal gate stack provide both threshold voltage control and drive current enhancement. This multi-functionality allows a single device structure to achieve application-specific optimization without requiring separate specialized devices, simplifying the manufacturing process while maintaining productivity benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CFET structure achieves a balance between speed and power consumption by employing high, standard, low, and ultra-low voltage threshold levels, optimizing performance for specific application needs while minimizing leakage and static power.
Implementation Method 1
respective ones of the plurality of stacked CFET devices include different combinations of N dipole doses and a P dipole dose in both the first metal gate stack and the second metal gate stack
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A stacked complementary field-effect device (CFET) device includes a bottom contact region and a top contact region. A plurality of stacked CFET devices is between the bottom contact region and the top contact region. Respective ones of the plurality of stacked CFET devices comprise a first transistor layer of a first type over the bottom contact region, and a second transistor layer of a second type over the first transistor layer. The first transistor layer comprises a first plurality of channels surrounded by a first metal gate stack, and the second transistor layer comprises a second plurality of channels surrounded by a second metal gate stack, wherein the respective ones of the plurality of stacked CFET devices include different combinations of N dipole doses and a P dipole dose in both the first metal gate stack and the second metal gate stack.