Ribbon-Supported Die Stacking for Smaller Semiconductor Packages
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Solution Overview
Problem
Conventional power semiconductor devices face challenges in reducing package size and footprint due to the substantial space taken by die pads and the limitations of ribbon patterns, which hinder efficient stacking of chips.
Innovation Solution
Utilizing ribbons as mounting surfaces for additional semiconductor chips by shaping them to have planar surfaces and employing them to support stacked chip configurations, allowing for reduced package dimensions and increased leadframe efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If ribbons are used solely for current channels, then electrical function is achieved, but mechanical support for stacking chips is insufficient
Solution Approach 1:
The patent makes ribbons serve dual functions: providing electrical current paths and serving as mechanical support structures for stacking chips. By shaping ribbons into planar surfaces and positioning them to contact chip surfaces, they simultaneously conduct electricity and mechanically support stacked configurations, eliminating the need for separate support structures.
Solution Approach 2:
The patent segments the ribbon structure into multiple planar surfaces at different positions and orientations. These segmented planar surfaces can independently support different chips in the stack, allowing each ribbon section to provide both electrical connection and mechanical support for specific chip layers.
2Area of stationary object
If chips are arranged side-by-side on leadframe, then assembly is simple, but package footprint is large
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement on the leadframe to a three-dimensional stacked configuration. Chips are arranged vertically in layers supported by ribbons, utilizing the vertical dimension to reduce the horizontal footprint while maintaining all necessary electrical connections through the ribbon structure.
3Strength
If ribbons are shaped to have planar surfaces for chip support, then mechanical support capability increases, but manufacturing complexity increases
Solution Approach 1:
The patent modifies ribbon parameters by creating planar surfaces through shaping processes that flatten specific sections of the ribbons. This parameter change from curved to planar surfaces provides adequate contact area for chip support while using standard metal forming techniques that are compatible with existing manufacturing processes.
Data Source
AI summary
A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.