Right-Hand Semiconductor Package Layout for Low-Parasitic Gate Loops
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving perfect symmetry and minimizing parasitic magnitude of the gate loop while maintaining DC+/DC− field cancellation and gate driver shielding, particularly in high-power electric converters using parallel connections of discrete packages.
Innovation Solution
The design of a right-hand semiconductor device with specific connector arrangements, including a control connector followed by a first load connector and a second load connector, forming a right-hand arrangement, and a mirrored package structure that reduces parasitic inductance and capacitance, allowing for easier paralleling of power transistors with a single gate driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If connectors are arranged in a conventional parallel configuration, then electrical clearance is maintained, but gate loop parasitic inductance increases
Solution Approach 1:
The patent applies asymmetry by introducing a right-hand arrangement where the second load connector (drain) is positioned as the thumb of the right hand, creating an asymmetric connector layout that optimizes the gate loop path. This asymmetric arrangement reduces gate loop parasitic inductance compared to conventional symmetric parallel configurations, while maintaining proper electrical clearance through carefully designed spacing relationships between connectors.
2Productivity
If multiple discrete packages are paralleled to increase output, then target output increases, but symmetry and parasitic magnitude trade-off deteriorates
Solution Approach 1:
The patent applies segmentation by providing both left-hand and right-hand semiconductor device variants with mirrored connector arrangements. This segmentation allows multiple discrete packages to be paralleled in a symmetric configuration where each device type maintains its optimized connector layout, enabling increased target output while preserving the symmetry and parasitic magnitude trade-off characteristics of individual devices.
Solution Approach 2:
The patent uses asymmetry within each segmented device (left-hand vs. right-hand variants) to optimize individual gate loop paths, while the overall parallel configuration maintains symmetry through complementary arrangement of opposite-handed devices, resolving the contradiction between increased output and maintained performance characteristics.
3Reliability
If connector spacing is increased for electrical clearance, then safety is improved, but gate loop area and parasitic inductance increase
Solution Approach 1:
The patent applies local quality by implementing different spacing relationships for different connector pairs within the same device. The control connector and load connectors are positioned with specific spacing that provides adequate electrical clearance where needed, while the gate loop path is optimized to minimize area. The right-hand arrangement creates localized optimal spacing that simultaneously satisfies both electrical clearance requirements and gate loop minimization goals.
Data Source
AI summary
A right-hand semiconductor device includes a control connector, a first load connector, and a second load connector, the connectors being arranged in the same plane and protruding out of a package of the semiconductor device, forming the fingers of a right-hand arrangement. The control connector is followed by the first load connector and the first load connector is followed by the second load connector. The second load connector is a thumb of the right-hand arrangement. The package includes a top side and a bottom side opposite the top side. The right-hand arrangement is seen from a topside view.